Memory disambiguation hardware to support software binary translation

Abstract

A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.

What is claimed is: 
     
       1. A processor comprising:
 a core to execute instructions, the instructions comprising memory operations, the core comprising: 
 a register file having a plurality of registers to store data for use in execution of the instructions; 
 a binary translator executed within the core to:
 determine a relative order of memory operations, 
 detect when a first memory operation has been reordered prior to a second memory operation with respect to an original order of memory operations, 
 identify a reordering problem of the first memory operation with respect to the second memory operation, by access to an alias tracking table that tracks at least two sequence numbers for each index, the at least two sequence numbers comprising a Maximum Load Sequence Number (MLSN) and a Last Store Sequence Number (LSSN), and 
 communicate the relative order of memory operations to the core; and 
 
 an alias hardware module to verify whether the memory operations are executed to distinct addresses. 
 
     
     
       2. The processor of  claim 1 , the instructions comprise a loop, where the loop is to be unrolled by a compiler coupled to the processor. 
     
     
       3. The processor of  claim 1 , the binary translator to assign a sequence number to each individual memory operation. 
     
     
       4. The processor of  claim 3 , the sequence number assigned to each individual memory operation comprises a push programmable sequence number (pushPSN). 
     
     
       5. The processor of  claim 1 , the alias hardware module to access:
 an alias information table as each individual memory operation is retired; and 
 an alias detection buffer as each individual memory operation is retired. 
 
     
     
       6. The processor of  claim 5 , the binary translator to use a hash function to index into the alias tracking table. 
     
     
       7. The processor of  claim 1 , the alias tracking table to update the MLSN and LSSN based on a sequence number of a current memory operation when the alias tracking table index is empty. 
     
     
       8. The processor of  claim 1 , the memory operations comprise load memory operations and store memory operations. 
     
     
       9. The processor of  claim 1 , the reordering problem comprises:
 at least one Read after Write (RAW) problem; 
 at least one Write after Read (WAR) problem; and/or 
 at least one Write after Write (WAW) problem. 
 
     
     
       10. A system comprising:
 a multi-core processor including:
 at least one core to execute instructions, the instructions comprising memory operations, the at least one core comprising:
 a register file having a plurality of registers to store data for use in execution of the instructions, 
 
 a binary translator to:
 determine a relative order of the memory operations, 
 assign a sequence number to each individual memory operation, the memory operations comprising the loop, 
 detect when a first memory operation has been reordered prior to a second memory operation with respect to an original order of the memory operations, 
 identify a reordering problem of the first memory operation with respect to the second memory operation, based on access to an alias tracking table having a plurality of indices each including at least two sequence numbers comprising a Maximum Load Sequence Number (MLSN) and a Last Store Sequence Number (LSSN), and 
 communicate the relative order of memory operations to the at least one core; and 
 
 an alias hardware module to verify whether the execution of memory operations are to distinct addresses; and 
 
 a dynamic random access memory (DRAM) coupled to the multi-core processor. 
 
     
     
       11. The system of  claim 10 , the sequence number assigned to each individual memory operation comprises a push programmable sequence number (pushPSN). 
     
     
       12. The system of  claim 10 , the alias hardware module to access an alias information table and an alias detection buffer as an individual memory operation is retired. 
     
     
       13. The system of  claim 12 , the binary translator to index into the alias tracking table. 
     
     
       14. The system of  claim 10 , the alias tracking table to update the MLSN and LSSN based on a sequence number of a current memory operation when the index of the alias tracking table is empty. 
     
     
       15. The system of  claim 10 , the memory operations comprise load memory operations and store memory operations. 
     
     
       16. The system of  claim 10 , the reordering problem comprises:
 at least one Read after Write (RAW) problem; 
 at least one Write after Read (WAR) problem; and/or 
 at least one Write after Write (WAW) problem. 
 
     
     
       17. A method comprising:
 unrolling a set of instructions to be executed within a processor, the set of instructions comprising memory operations; 
 determining an original order of the memory operations; 
 detecting when a first memory operation has been reordered prior to a second memory operation with respect to the original order of the memory operations; 
 identifying a reordering problem of the first memory operation with respect to the second memory operation, based on access to an alias tracking table to store at least two sequence numbers comprising a Maximum Load Sequence Number (MLSN) and a Last Store Sequence Number (LSSN) per index; 
 addressing the reordering problem; and 
 communicating a relative order of the memory operations to the processor. 
 
     
     
       18. The method of  claim 17 , communicating the relative order of the memory operations to the processor further comprising:
 conveying the relative order of the memory operations to the processor when the set of instructions has been executed; 
 accessing an alias information table and an alias detection buffer; and 
 computing checks on each memory operation as directed by the alias information table as an individual memory operation is retired.