Inventor

GAJERA NEVIL N

US47 patents

⚠️ This page may combine multiple inventors who share the name “GAJERA NEVIL N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GAJERA NEVIL N

MICRON TECHNOLOGY INC

Multi-state programming of memory cells

Identify the programming mode of memory cells during reading of the memory cells

Multi-step pre-read for write operations in memory devices

Data-based polarity write operations

Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells

Read refresh operation

Adaptively programming memory cells in different modes to optimize performance

Bipolar read retry

Evaluation of background leakage to select write voltage in memory devices

Accessing a multi-level memory cell

Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells

Drift aware read operations

Multi-step pre-read for write operations in memory devices

Memory cell read operation techniques

Identify the programming mode of memory cells during reading of the memory cells

Evaluation of background leakage to select write voltage in memory devices

Weighted wear leveling for improving uniformity

Systems and methods for pre-read scan of memory devices

Multi-state programming of memory cells

Bipolar read retry

Data-based polarity write operations

Three-dimensional memory arrays, and methods of forming the same

Selective inhibition of memory

Adjustable programming pulses for a multi-level cell

Dynamic read voltage techniques

Drift aware read operations

Conditional drift cancellation operations in programming memory cells to store data

Sense lines in three-dimensional memory arrays, and methods of forming the same

Performing refresh operations on memory cells

Cache memory with randomized eviction

Cache memory with randomized eviction

Self-selecting memory cells configured to store more than one bit per memory cell

Programming intermediate state to store data in self-selecting memory cells

Performing refresh operations of non-volatile memory to mitigate read disturb

Accessing a multi-level memory cell

Memory operation with double-sided asymmetric decoders

Memory operation with double-sided asymmetric decoders

Apparatus including an array of pre-configurable memory and storage

Data correction scheme with reduced device overhead

INTEL CORP

Techniques to mitigate bias drift for a memory device

Method and apparatus for adjusting demarcation voltages based on cycle count metrics

Multistage set procedure for phase change memory

Multistage set procedure for phase change memory

Techniques to mitigate bias drift for a memory device

Multistage set procedure for phase change memory

Multistage set procedure for phase change memory

Techniques to mitigate bias drift for a memory device