Multi-state programming of memory cells

Abstract

The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of four possible data states by applying a first voltage pulse to the memory cell wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell wherein the second voltage pulse has a second polarity and a second magnitude, and the second voltage pulse is applied for a shorter duration than the first voltage pulse.

What is claimed is: 
     
       1. An apparatus, comprising:
 a memory; and 
 circuitry configured to program a memory cell of the memory to one of four possible data states by:
 applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity; and 
 applying a second voltage pulse to the memory cell, wherein:
 the second voltage pulse has a second polarity; and 
 the second voltage pulse is applied for a shorter duration than the first voltage pulse; and 
 
 wherein a magnitude of a threshold voltage distribution associated with a first one of the four possible data states is less than a magnitude of a threshold voltage distribution associated with a second one of the four possible data states. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the first polarity is one of a positive polarity or a negative polarity and the second polarity is the other one of the positive polarity or the negative polarity. 
     
     
       3. The apparatus of  claim 2 , wherein the memory cell is programmed to the first one of the four possible data states when the first voltage pulse has the positive polarity. 
     
     
       4. The apparatus of  claim 2 , wherein the memory cell is programmed to the second one of the four possible data states when the first voltage pulse has the positive polarity and the second voltage pulse has the negative polarity. 
     
     
       5. The apparatus of  claim 2 , wherein the memory cell is programmed to a third one of the four possible data states when the first voltage pulse has the negative polarity and the second voltage pulse has the positive polarity. 
     
     
       6. The apparatus of  claim 2 , wherein the memory cell is programmed to a fourth one of the four possible data states when the first voltage pulse has the negative polarity. 
     
     
       7. The apparatus of  claim 1 , wherein each of the four possible data states corresponds to a different threshold voltage distribution. 
     
     
       8. The apparatus of  claim 1 , wherein a magnitude of a threshold voltage distribution associated with a third one of the four possible data states is less than a magnitude of a threshold voltage distribution associated with a fourth one of the four possible data states. 
     
     
       9. The apparatus of  claim 8 , wherein a difference between the threshold voltage distribution associated with the first one of the four possible data states and the threshold voltage distribution associated with the fourth one of the four possible data states is greater than a difference between the threshold voltage distribution associated with the second one of the four possible data states and the threshold voltage distribution associated with the third one of the four possible data states. 
     
     
       10. The apparatus of  claim 1 , wherein a magnitude of a threshold voltage of the memory cell increases when the second voltage pulse is applied to the memory cell. 
     
     
       11. An apparatus, comprising:
 a memory; and 
 circuitry configured to program a memory cell of the memory to one of four possible data states by:
 applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first magnitude; and 
 applying a second voltage pulse to the memory cell, wherein:
 the second voltage pulse has a second magnitude that is less than the first magnitude; and 
 the second voltage pulse is applied for a shorter duration than the first voltage pulse. 
 
 
 
     
     
       12. The apparatus of  claim 11 , wherein the first voltage pulse is applied for twice the duration of the second voltage pulse. 
     
     
       13. The apparatus of  claim 11 , wherein the first magnitude of the first voltage pulse is in a first range of voltage magnitudes that is greater than a second range of voltage magnitudes in which the second magnitude of the second voltage pulse is in. 
     
     
       14. The apparatus of  claim 13 , wherein a minimum voltage magnitude of the first range of voltage magnitudes is less than a maximum voltage magnitude of the second range of voltage values. 
     
     
       15. The apparatus of  claim 11 , wherein the second magnitude is at least 50% of the first magnitude. 
     
     
       16. A method, comprising:
 programming a memory cell to one of four possible data states by:
 applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude; and 
 applying a second voltage pulse to the memory cell, wherein:
 the second voltage pulse has a second polarity and a second magnitude; and 
 the first magnitude is a different magnitude than the second magnitude. 
 
 
 
     
     
       17. The method of  claim 16 , wherein the memory cell is programmed to a first one of the four possible data states or a fourth one of the four possible data states after the first voltage pulse is applied to the memory cell and before the second voltage pulse is applied to the memory cell. 
     
     
       18. The method of  claim 16 , wherein the memory cell is programmed to a second one of the four possible data states or a third one of the four possible data states after the first voltage pulse and the second voltage pulse are applied to the memory cell.