P

Inventor

GOULD SCOTT W

US24 patents

Patents

24 patents
US5552721ASep 3, 1996

Method and system for enhanced drive in programmmable gate arrays

IBM165 citations99
US6883152B2Apr 19, 2005

Voltage island chip implementation

IBM92 citations98
US6820240B2Nov 16, 2004

Voltage island chip implementation

IBM90 citations98
US6779163B2Aug 17, 2004

Voltage island design planning

IBM89 citations98
US6397170B1May 28, 2002

Simulation based power optimization

IBM110 citations98
US5631578AMay 20, 1997

Programmable array interconnect network

IBM212 citations96
US6598206B2Jul 22, 2003

Method and system of modifying integrated circuit power rails

IBM52 citations94
US7096436B2Aug 22, 2006

Macro design techniques to accommodate chip level wiring and circuit placement across the macro

IBM32 citations92
US6802033B1Oct 5, 2004

Low-power critical error rate communications controller

IBM42 citations92
US6543040B1Apr 1, 2003

Macro design techniques to accommodate chip level wiring and circuit placement across the macro

IBM18 citations92
US6490708B2Dec 3, 2002

Method of integrated circuit design by selection of noise tolerant gates

IBM24 citations92
US6425092B1Jul 23, 2002

Method and apparatus for preventing thermal failure in a semiconductor device through redundancy

IBM33 citations92
US6237132B1May 22, 2001

Toggle based application specific core methodology

IBM33 citations92
US5341310AAug 23, 1994

Wiring layout design method and system for integrated circuits

IBM34 citations92
US6493859B1Dec 10, 2002

Method of wiring power service terminals to a power network in a semiconductor integrated circuit

IBM36 citations91
US7496877B2Feb 24, 2009

Electrostatic discharge failure avoidance through interaction between floorplanning and power routing

IBM9 citations83
US7234124B2Jun 19, 2007

Method and apparatus for performing power routing on a voltage island within an integrated circuit chip

IBM12 citations82
US7131074B2Oct 31, 2006

Nested voltage island architecture

IBM10 citations74
US6825711B2Nov 30, 2004

Power reduction by stage in integrated circuit

IBM12 citations74
US6883155B2Apr 19, 2005

Macro design techniques to accommodate chip level wiring and circuit placement across the macro

IBM7 citations73
US6134704AOct 17, 2000

Integrated circuit macro apparatus

IBM9 citations73
US6861753B1Mar 1, 2005

Method and apparatus for performing power routing on a voltage island within an integrated circuit chip

IBM5 citations71
US7289659B2Oct 30, 2007

Method and apparatus for manufacturing diamond shaped chips

IBM2 citations63
US7961932B2Jun 14, 2011

Method and apparatus for manufacturing diamond shaped chips

IBM1 citations52