Inventor

LEE YUEH-CHUAN

TW46 patents

⚠️ This page may combine multiple inventors who share the name “LEE YUEH-CHUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE YUEH-CHUAN

TAIWAN SEMICONDUCTOR MFG CO LTD

Backside illuminated (BSI) image sensor with a reflector

Pixel with raised photodiode structure

Method for forming image sensor device

Photosensing pixel including self-aligned light shielding layer

Storage node light shield for pixel of image sensor

Image sensor with shallow trench edge doping

Apparatus and methods for effective impurity gettering

Image sensor with shallow trench edge doping

Bond pad structure for bonding improvement

Semiconductor arrangement and method for making

Image sensor with shallow trench edge doping

Image sensor with shallow trench edge doping

Device comprising photodiode and method of making the same

Bond pad structure for bonding improvement

Image sensor with shallow trench edge doping

CMOS image sensor with shallow trench edge doping

Bond pad structure for bonding improvement

Method for wafer dicing

Wafer structure and method for wafer dicing

Method for fabricating image sensor device

Image sensor device

Mechanisms for forming image sensor with lateral doping gradient

Protected chip-scale package (CSP) pad structure

Device comprising photodiode and method of making the same

Protected chip-scale package (CSP) pad structure

Protected chip-scale package (CSP) pad structure

Test line structure and method for performing wafer acceptance test

Complementary metal-oxide-semiconductor (CMOS) image sensor with silicon and silicon germanium

Pixel with transistor gate covering photodiode

Backside illuminated image sensor device structure

PROMOS TECHNOLOGIES INC

Method of forming self-aligned contact structure with locally etched gate conductive layer

[DRAM structure and fabricating method thereof]

Method of manufacturing deep trench capacitor

Shallow trench isolation structure and dynamic random access memory, and fabricating methods thereof

Deep-trench capacitor with hemispherical grain silicon surface and method for making the same

Deep-trench capacitor with hemispherical grain silicon surface and method for making the same

Semiconductor structure with lining layer partially etched on sidewall of the gate

Volatile memory structure and method for forming the same

DRAM structure and fabricating method thereof

Volatile memory devices and methods for forming same

Trench capacitors with buried isolation layer formed by an oxidation process and methods for manufacturing the same

NAT SCIENCE COUNCIL

Process for preparing Cu damascene interconnection

Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method

Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure

Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure

(unassigned)

Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition