Inventor
GEHRING ANDREAS
DE21 patents
⚠️ This page may combine multiple inventors who share the name “GEHRING ANDREAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ADVANCED MICRO DEVICES INC
6 patentsUS7754556B2Jul 13, 2010
Reducing transistor junction capacitance by recessing drain and source regions
ADVANCED MICRO DEVICES INC18 citations92
US7943442B2May 17, 2011
SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device
ADVANCED MICRO DEVICES INC9 citations84
US7713763B2May 11, 2010
Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions
ADVANCED MICRO DEVICES INC6 citations73
US7772077B2Aug 10, 2010
Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region
ADVANCED MICRO DEVICES INC2 citations62
US8377761B2Feb 19, 2013
SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device
ADVANCED MICRO DEVICES INC1 citations52
US7816199B2Oct 19, 2010
Method of forming a semiconductor structure comprising an implantation of ions of a non-doping element
ADVANCED MICRO DEVICES INC0 citations41
GLOBALFOUNDRIES INC
5 patentsUS7763505B2Jul 27, 2010
Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations
GLOBALFOUNDRIES INC18 citations84
US7939399B2May 10, 2011
Semiconductor device having a strained semiconductor alloy concentration profile
GLOBALFOUNDRIES INC7 citations80
US7790537B2Sep 7, 2010
Method for creating tensile strain by repeatedly applied stress memorization techniques
GLOBALFOUNDRIES INC4 citations62
US7754555B2Jul 13, 2010
Transistor having a channel with biaxial strain induced by silicon/germanium in the gate electrode
GLOBALFOUNDRIES INC5 citations62
US7897451B2Mar 1, 2011
Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors
GLOBALFOUNDRIES INC1 citations52
MOWRY ANTHONY
3 patentsUS8227266B2Jul 24, 2012
Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions
MOWRY ANTHONY6 citations83
US8093634B2Jan 10, 2012
In situ formed drain and source regions in a silicon/germanium containing transistor device
MOWRY ANTHONY9 citations82
US8530894B2Sep 10, 2013
Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions
MOWRY ANTHONY0 citations51
GEHRING ANDREAS
2 patentsUS8652913B2Feb 18, 2014
Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss
GEHRING ANDREAS0 citations47
US8129236B2Mar 6, 2012
Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode
GEHRING ANDREAS1 citations47