Inventor
LIN ZIYIN
US8 patents
Patents
8 patentsUS11688634B2Jun 27, 2023
Trenches in wafer level packages for improvements in warpage reliability and thermals
INTEL CORP2 citations71
US11282717B2Mar 22, 2022
Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap
INTEL CORP2 citations69
US12068222B2Aug 20, 2024
Dummy die structures of a packaged integrated circuit device
INTEL CORP1 citations59
US11776821B2Oct 3, 2023
Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap
INTEL CORP0 citations59
US11749585B2Sep 5, 2023
High thermal conductivity, high modulus structure within a mold material layer of an integrated circuit package
INTEL CORP0 citations59
US12130482B2Oct 29, 2024
Hydrophobic feature to control adhesive flow
INTEL CORP0 citations57
US11676876B2Jun 13, 2023
Semiconductor die package with warpage management and process for forming such
INTEL CORP0 citations57
US12002727B2Jun 4, 2024
Barrier structures for underfill containment
INTEL CORP0 citations44