Inventor

SARANGDHAR NITIN V

US52 patents

⚠️ This page may combine multiple inventors who share the name “SARANGDHAR NITIN V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SARANGDHAR NITIN V

INTEL CORP

Apparatus and method for caching lock conditions in a multi-processor system

Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue

Computer system with distributed bus arbitration scheme for symmetric and priority agents

Apparatus and method for performing error correction in a multi-processor system

Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management

Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches

Method and apparatus for performing deferred transactions

Method and apparatus for cache memory replacement line identification

Highly pipelined bus architecture

Method and apparatus for determining the timing of snoop windows in a pipelined bus

Apparatus and method of maintaining processor ordering in a multiprocessor system which includes one or more processors that execute instructions speculatively

Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system

Computer system that maintains system wide cache coherency during deferred communication transactions

Write combining buffer for sequentially addressed partial line operations originating from a single instruction

Method and apparatus for performing deferred transactions

Method and apparatus for performing bus transactions in a computer system

Method and apparatus for snoop stretching using signals that convey snoop results

Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems

Method and apparatus for performing deferred transactions

Method and apparatus for ordering writeback data transfers on a bus

Method and apparatus for performing bus transactions in a computer system

Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair

Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency

Method and apparatus for self-snooping a bus during a boundary transaction

Method and apparatus for transferring information between a processor and a memory system

Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency

Bus patcher

Bus patcher

Trusted platform module certification and attestation utilizing an anonymous key system

Trusted platform module certification and attestation utilizing an anonymous key system

Iris recognition including liveness testing

Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth

Method and apparatus for accessing split lock variables in a computer system

Privacy protected input-output port control

In-system provisioning of firmware for a hardware platform

Data flow control mechanism for a bus supporting two-and three-agent transactions

Technologies for end-to-end biometric-based authentication and platform locality assertion

In-system provisioning of firmware for a hardware platform

Versatile protected input/output device access and isolated servicing for virtual machines

Trusted launch of secure enclaves in virtualized environments

Secure replay protected storage

Using counters and a table to protect data in a storage device

Additional secured execution environment with SR-IOV and xHCI-IOV

Infrared light emitting diode control circuit

Technologies for end-to-end biometric-based authentication and platform locality assertion

Protecting a memory device from becoming unusable

SARANGDHAR NITIN V

Enhanced privacy ID based platform attestation

Secure replay protected storage

Protecting keystrokes received from a keyboard in a platform containing embedded controllers

SINGHAL ABHISHEK

Audio subsystem sharing in a virtualized environment