Inventor

DELACRUZ JAVIER A

US119 patents

⚠️ This page may combine multiple inventors who share the name “DELACRUZ JAVIER A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DELACRUZ JAVIER A

INVENSAS BONDING TECH INC

Cavity packages

Bonded structures

Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein

Bonded structures

Increased contact alignment tolerance for direct bonding

Bonded structures without intervening adhesive

Protective elements for bonded structures

Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes

Wafer-level bonding of obstructive elements

Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects

Interface structures and methods for forming same

Increased contact alignment tolerance for direct bonding

Security circuitry for bonded structures

Bonded structures

Bonded structures

Bonded structures

INVENSAS CORP

Dielets on flexible and stretchable packaging for microelectronics

Mixed exposure for large die

Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

Wire bonding method and apparatus for electromagnetic interference shielding

Symbiotic network on layers

Network on layer enabled architectures

Wire bonding method and apparatus for electromagnetic interference shielding

Embedded organic interposers for high bandwidth

Surface integrated waveguides and circuit structures therefor

Flipped die stacks with multiple rows of leadframe interconnects

Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC

Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects

Protective elements for bonded structures

Directly bonded structures without intervening adhesive and methods for forming the same

Wafer-level bonding of obstructive elements

Circuitry for electrical redundancy in bonded structures

Bonded structures

Bonded structures with integrated passive component

Protective elements for bonded structures including an obstructive element

Cavity packages

Circuitry for electrical redundancy in bonded structures

Bonded structures

XCELSIS CORP

Systems and methods for releveled bump planes for chiplets

Transistor level interconnection methodologies utilizing 3D interconnects

Hard IP blocks with physically bidirectional passageways

Back biasing of FD-SOI circuit blocks

Systems and methods for releveled bump planes for chiplets

Direct-bonded native interconnects and active base die

Direct-bonded native interconnects and active base die

Device disaggregation for improved performance

ADEIA SEMICONDUCTOR INC

Integrated voltage regulator and passive components

Device disaggregation for improved performance

ADEIA SEMICONDUCTOR TECH LLC

Apparatus for non-volatile random access memory stacks

Scalable architecture for reduced cycles across SOC