Inventor
FISCH DAVID EDWARD
US23 patents
⚠️ This page may combine multiple inventors who share the name “FISCH DAVID EDWARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XCELSIS CORP
6 patentsUS10991804B2Apr 27, 2021
Transistor level interconnection methodologies utilizing 3D interconnects
XCELSIS CORP144 citations99
US11127738B2Sep 21, 2021
Back biasing of FD-SOI circuit blocks
XCELSIS CORP144 citations97
US10522352B2Dec 31, 2019
Direct-bonded native interconnects and active base die
XCELSIS CORP20 citations94
US10832912B2Nov 10, 2020
Direct-bonded native interconnects and active base die
XCELSIS CORP10 citations93
US11289333B2Mar 29, 2022
Direct-bonded native interconnects and active base die
XCELSIS CORP1 citations73
US10684929B2Jun 16, 2020
Self healing compute array
XCELSIS CORP0 citations52
INVENSAS CORP
6 patentsUS9812185B2Nov 7, 2017
DRAM adjacent row disturb mitigation
INVENSAS CORP69 citations98
US10262717B2Apr 16, 2019
DRAM adjacent row disturb mitigation
INVENSAS CORP10 citations84
US9007866B2Apr 14, 2015
Retention optimized memory device using predictive data inversion
INVENSAS CORP5 citations82
US9299398B2Mar 29, 2016
Retention optimized memory device using predictive data inversion
INVENSAS CORP1 citations61
US9548101B2Jan 17, 2017
Retention optimized memory device using predictive data inversion
INVENSAS CORP0 citations51
US10164633B2Dec 25, 2018
On-chip impedance network with digital coarse and analog fine tuning
INVENSAS CORP0 citations47
ADEIA SEMICONDUCTOR INC
4 patentsUS11823906B2Nov 21, 2023
Direct-bonded native interconnects and active base die
ADEIA SEMICONDUCTOR INC2 citations73
US11688776B2Jun 27, 2023
Transistor level interconnection methodologies utilizing 3D interconnects
ADEIA SEMICONDUCTOR INC2 citations73
US12362182B2Jul 15, 2025
Direct-bonded native interconnects and active base die
ADEIA SEMICONDUCTOR INC0 citations62
US12272730B2Apr 8, 2025
Transistor level interconnection methodologies utilizing 3D interconnects
ADEIA SEMICONDUCTOR INC0 citations62
FISCH DAVID EDWARD
3 patentsUS8618647B2Dec 31, 2013
Packaged microelectronic elements having blind vias for heat dissipation
FISCH DAVID EDWARD2 citations60
US8873302B2Oct 28, 2014
Common doped region with separate gate control for a logic compatible non-volatile memory cell
FISCH DAVID EDWARD3 citations59
US9230814B2Jan 5, 2016
Non-volatile memory devices having vertical drain to gate capacitive coupling
FISCH DAVID EDWARD0 citations37