Inventor
SIRASAO ASHISH
US40 patents
Patents
40 patentsUS10515135B1Dec 24, 2019
Data format suitable for fast massively parallel general matrix multiplication in a programmable IC
XILINX INC25 citations94
US10460416B1Oct 29, 2019
Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit
XILINX INC19 citations94
US10354733B1Jul 16, 2019
Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC
XILINX INC40 citations94
US11204747B1Dec 21, 2021
Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions
XILINX INC19 citations93
US10572409B1Feb 25, 2020
Sparse matrix processing circuitry
XILINX INC54 citations93
US10572225B1Feb 25, 2020
Circuit arrangements and methods for performing multiply-and-accumulate operations
XILINX INC26 citations93
US10331836B1Jun 25, 2019
Loop optimization for implementing circuit designs in hardware
XILINX INC20 citations91
US11449347B1Sep 20, 2022
Time-multiplexed implementation of hardware accelerated functions in a programmable integrated circuit
XILINX INC7 citations85
US11222256B2Jan 11, 2022
Neural network processing system having multiple processors and a neural network accelerator
XILINX INC8 citations85
US10943039B1Mar 9, 2021
Software-driven design optimization for fixed-point multiply-accumulate circuitry
XILINX INC11 citations85
US10678509B1Jun 9, 2020
Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators
XILINX INC11 citations85
US11106968B1Aug 31, 2021
Circuit arrangements and methods for traversing input feature maps
XILINX INC7 citations84
US11036827B1Jun 15, 2021
Software-defined buffer/transposer for general matrix multiplication in a programmable IC
XILINX INC7 citations84
US10411709B1Sep 10, 2019
Circuit arrangements and methods for dividing a three-dimensional input feature map
XILINX INC13 citations84
US8769450B1Jul 1, 2014
Synthesis flow for formal verification
XILINX INC9 citations84
US10747502B2Aug 18, 2020
Multiply and accumulate circuit
XILINX INC13 citations83
US9875330B2Jan 23, 2018
Folding duplicate instances of modules in a circuit design
XILINX INC7 citations83
US8667436B1Mar 4, 2014
Object identification in an electronic circuit design
XILINX INC6 citations83
US10936311B1Mar 2, 2021
Sparse matrix processing circuitry
XILINX INC8 citations81
US10990826B1Apr 27, 2021
Object detection in video
XILINX INC9 citations79
US12086572B1Sep 10, 2024
Software defined neural network layer pipelining
XILINX INC6 citations75
US11568218B2Jan 31, 2023
Neural network processing system having host controlled kernel acclerators
XILINX INC5 citations74
US11429848B2Aug 30, 2022
Host-directed multi-layer neural network processing via per-layer work requests
XILINX INC4 citations73
US11386644B2Jul 12, 2022
Image preprocessing for generalized image processing
XILINX INC2 citations73
US10984500B1Apr 20, 2021
Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit
XILINX INC3 citations73
US11620490B2Apr 4, 2023
Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions
XILINX INC3 citations72
US10824434B1Nov 3, 2020
Dynamically structured single instruction, multiple data (SIMD) instructions
XILINX INC2 citations72
US10678983B1Jun 9, 2020
Local retiming optimization for circuit designs
XILINX INC2 citations72
US10430539B1Oct 1, 2019
Method and apparatus for enhancing performance by moving or adding a pipelined register stage in a cascaded chain
XILINX INC5 citations72
US9460253B1Oct 4, 2016
Selecting predefined circuit implementations in a circuit design system
XILINX INC3 citations72
US9268891B1Feb 23, 2016
Compact and efficient circuit implementation of dynamic ranges in hardware description languages
XILINX INC3 citations72
US10990736B1Apr 27, 2021
Implementing a circuit design with re-convergence
XILINX INC2 citations71
US10303833B1May 28, 2019
Parallelizing timing-based operations for circuit designs
XILINX INC6 citations71
US9235498B1Jan 12, 2016
Circuits for and methods of enabling the modification of an input data stream
XILINX INC5 citations69
US10289786B1May 14, 2019
Circuit design transformation for automatic latency reduction
XILINX INC1 citations60
US11188697B1Nov 30, 2021
On-chip memory access pattern detection for power and resource reduction
XILINX INC0 citations59
US12061990B2Aug 13, 2024
Static block scheduling in massively parallel software defined hardware systems
XILINX INC0 citations52
US11694066B2Jul 4, 2023
Machine learning runtime library for neural network acceleration
XILINX INC0 citations51
US10726175B1Jul 28, 2020
Systems for optimization of read-only memory (ROM)
XILINX INC0 citations50
US8938700B1Jan 20, 2015
Data-driven pattern matching in synthesis of circuit designs
XILINX INC1 citations50