Inventor

HOU SHANG-YUN

TW242 patents

⚠️ This page may combine multiple inventors who share the name “HOU SHANG-YUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOU SHANG-YUN

TAIWAN SEMICONDUCTOR MFG CO LTD

Tri-layer CoWoS structure

Package structures and methods of forming the same

Structure and formation method for chip package

Chip package having die structures of different heights and method of forming same

Photonic semiconductor device and method of manufacture

Interconnect chips

Interconnect chips

Chip package having die structures of different heights

Testing of semiconductor chips with microbumps

Stacked integrated circuit structure and method of forming

3D semiconductor package interposer with die cavity

Testing of semiconductor chips with microbumps

Thermal structure for integrated circuit package

Packages with interposers and methods for forming the same

Photonic semiconductor device and method of manufacture

Semiconductor device, electronic device including the same, and manufacturing method thereof

Package structures and methods of forming the same

Package and manufacturing method thereof

Chip package having die structures of different heights and method of forming same

Semiconductor die package and method of manufacture

Giga interposer integration through chip-on-wafer-on-substrate

Photonic semiconductor device and method

TAIWAN SEMICONDUCTOR MFG

Testing of semiconductor chips with microbumps

3D packages and methods for forming the same

Package with metal-insulator-metal capacitor and method of manufacturing the same

Structure and method for 3D IC package

3D packages and methods for forming the same

3D semiconductor package interposer with die cavity

Testing of semiconductor chips with microbumps

3D semiconductor package interposer with die cavity

Heat spreader structures in scribe lines

Metal electrical fuse structure

3D packages and methods for forming the same

Seal ring in semiconductor device

Method for forming high reliability bump structure

Three dimensional integrated circuits stacking approach

JENG SHIN-PUU

3D semiconductor package interposer with die cavity

Seal ring structure with improved cracking protection

Protective seal ring for preventing die-saw induced stress

Passivation layer for packaged chip

YU CHEN-HUA

Packages with passive devices and methods of forming the same

Interposer system and method

Connector design for packaging integrated circuits

WU WEI-CHENG

Package systems having interposers

Testing of semiconductor chips with microbumps

Semiconductor device having pad structure with stress buffer layer

HU HSIEN-PIN

Approach for bonding dies onto interposers

Approach for bonding dies onto interposers

Approach for bonding dies onto interposers

LIU TZUAN-HORNG

Interposer test structures and methods