Inventor
BARRY EDWIN FRANKLIN
US44 patents
⚠️ This page may combine multiple inventors who share the name “BARRY EDWIN FRANKLIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
22 patentsUS7945760B1May 17, 2011
Methods and apparatus for address translation functions
ALTERA CORP19 citations93
US7809932B1Oct 5, 2010
Methods and apparatus for adapting pipeline stage latency based on instruction type
ALTERA CORP23 citations93
USRE40883EAug 25, 2009
Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision
ALTERA CORP26 citations93
US7257696B2Aug 14, 2007
Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions
ALTERA CORP14 citations92
US7146487B2Dec 5, 2006
Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution
ALTERA CORP29 citations92
US7237088B2Jun 26, 2007
Methods and apparatus for providing context switching between software tasks with reconfigurable control
ALTERA CORP14 citations84
US7386710B2Jun 10, 2008
Methods and apparatus for scalable array processor interrupt detection and response
ALTERA CORP4 citations74
US7765338B2Jul 27, 2010
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
ALTERA CORP4 citations73
US7266620B1Sep 4, 2007
System core for transferring data between an external device and memory
ALTERA CORP5 citations73
US7853779B2Dec 14, 2010
Methods and apparatus for scalable array processor interrupt detection and response
ALTERA CORP2 citations63
USRE41904EOct 26, 2010
Methods and apparatus for providing direct memory access control
ALTERA CORP2 citations63
USRE41012ENov 24, 2009
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor
ALTERA CORP4 citations63
US7272700B1Sep 18, 2007
Methods and apparatus for indirect compound VLIW execution using operand address mapping techniques
ALTERA CORP5 citations63
US7254695B2Aug 7, 2007
Coprocessor processing instructions in turn from multiple instruction ports coupled to respective processors
ALTERA CORP2 citations63
US7130934B2Oct 31, 2006
Methods and apparatus for providing data transfer control
ALTERA CORP2 citations63
US9442872B2Sep 13, 2016
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
ALTERA CORP1 citations62
US7506137B2Mar 17, 2009
Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions
ALTERA CORP2 citations62
US7908409B2Mar 15, 2011
Methods and apparatus for providing data transfer control
ALTERA CORP0 citations52
US7627698B2Dec 1, 2009
Methods and apparatus for providing data transfer control
ALTERA CORP0 citations52
USRE40213EApr 1, 2008
Methods and apparatus for providing direct memory access control
ALTERA CORP0 citations52
US7302504B2Nov 27, 2007
Methods and apparatus for providing data transfer control
ALTERA CORP0 citations52
US9009365B2Apr 14, 2015
System core for transferring data between an external device and memory
ALTERA CORP0 citations51
BARRY EDWIN FRANKLIN
13 patentsUS8489858B2Jul 16, 2013
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN5 citations84
US8156261B2Apr 10, 2012
Methods and apparatus for providing data transfer control
BARRY EDWIN FRANKLIN3 citations73
US9329866B2May 3, 2016
Methods and apparatus for adapting pipeline stage latency based on instruction type
BARRY EDWIN FRANKLIN2 citations63
US9158547B2Oct 13, 2015
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN1 citations63
US8413086B2Apr 2, 2013
Methods and apparatus for adapting pipeline stage latency based on instruction type
BARRY EDWIN FRANKLIN3 citations63
US8082372B2Dec 20, 2011
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
BARRY EDWIN FRANKLIN1 citations62
US7975080B2Jul 5, 2011
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
BARRY EDWIN FRANKLIN1 citations62
US8751772B2Jun 10, 2014
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN0 citations52
US8713284B1Apr 29, 2014
Methods and apparatus for address translation functions
BARRY EDWIN FRANKLIN0 citations52
US8255664B2Aug 28, 2012
Methods and apparatus for address translation functions
BARRY EDWIN FRANKLIN0 citations52
US8161267B2Apr 17, 2012
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN0 citations52
US8601176B2Dec 3, 2013
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
BARRY EDWIN FRANKLIN0 citations51
US8244931B2Aug 14, 2012
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
BARRY EDWIN FRANKLIN0 citations51
PECHANEK GERALD GEORGE
4 patentsUS9063722B2Jun 23, 2015
Methods and apparatus for independent processor node operations in a SIMD array processor
PECHANEK GERALD GEORGE3 citations63
US8296479B2Oct 23, 2012
System core for transferring data between an external device and memory
PECHANEK GERALD GEORGE1 citations62
US8103854B1Jan 24, 2012
Methods and apparatus for independent processor node operations in a SIMD array processor
PECHANEK GERALD GEORGE0 citations52
US8397000B2Mar 12, 2013
System core for transferring data between an external device and memory
PECHANEK GERALD GEORGE0 citations51
PTS CORP
3 patentsUS6851041B2Feb 1, 2005
Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
PTS CORP29 citations92
US6912608B2Jun 28, 2005
Methods and apparatus for pipelined bus
PTS CORP12 citations83
US7058790B2Jun 6, 2006
Cascaded event detection modules for generating combined events interrupt for processor action
PTS CORP4 citations63