Inventor

BASKER VEERARAGHAVAN

US22 patents

⚠️ This page may combine multiple inventors who share the name “BASKER VEERARAGHAVAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BASKER VEERARAGHAVAN

IBM

Self-aligned punch through stopper liner for bulk FinFET

Method of forming source/drain contacts in unmerged FinFETs

Nanosheet bottom isolation and source or drain epitaxial growth

Self-aligned punch through stopper liner for bulk FinFET

Integrated FinFET capacitor

Replacement gate cross-couple for static random-access memory scaling

Partial self-aligned contact for MOL

Nanosheet transistor having partially self-limiting bottom isolation extending into the substrate and under the source/drain and gate regions

Gate contact over active enabled by alternative spacer scheme and claw-shaped cap

Partial self-aligned contact for MOL

Vertical transistor including symmetrical source/drain extension junctions

Vertical transistor including symmetrical source/drain extension junctions

Integrated FinFET capacitor

Method of source/drain height control in dual epi finFET formation

Contact interlayer dielectric replacement with improved SAC cap retention

Self-aligned punch through stopper liner for bulk FinFET

Self-aligned punch through stopper liner for bulk FinFET

GLOBALFOUNDRIES INC

Buried local interconnect in finfet structure and method of fabricating same

Methods of forming contact structures on integrated circuit products

Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device

Contact structures for integrated circuit products

Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device