Self-aligned punch through stopper liner for bulk FinFET

Abstract

A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.

What is claimed is: 
     
       1. A self-aligned field effect transistor structure, comprising:
 a bulk substrate having a plurality of fins patterned therein; 
 an n-type field effect transistor region formed of at least one of the plurality of fins patterned on the substrate, the n-type field effect transistor region having a boron doped layer formed on a portion of the fin and a first hardmask layer formed on the boron doped layer of the n-type field effect transistor region; 
 a p-type field effect transistor region formed of at least one of the plurality of fins patterned on the substrate, the p-type field effect transistor region having a phosphorous or arsenic doped layer formed on a portion of the fin and a second hardmask layer formed on the phosphorous or arsenic doped layer of the p-type field effect transistor region, wherein the phosphorous or arsenic doped layer is in direct contact with the portion of the fin; 
 a boundary region between the n-type field effect transistor region and the p-type field effect transistor region comprising an insulator material disposed between the n-type field effect transistor region and the p-type field effect transistor region such that there is a separation between the boron doped layer of the n-type field effect transistor region and the phosphorous or arsenic doped layer of the p-type field effect transistor region; 
 wherein the boron doped layer and the phosphorous or arsenic doped layer do not physically contact each other; 
 wherein the insulator material is disposed between the first hardmask layer and the second hardmask layer; 
 wherein the insulator material does not physically contact the plurality of fins; and 
 wherein the insulator material is in physical contact with the bulk substrate in the boundary region. 
 
     
     
       2. The self-aligned field effect transistor structure of  claim 1 , wherein the at least one of the plurality of fins forming the p-type field effect transistor region comprises a silicon germanium material. 
     
     
       3. The self-aligned field effect transistor structure of  claim 1 , wherein an unrevealed portion of the at least one of the plurality of fins forming the p-type field effect transistor region is doped with a phosphorous type dopant. 
     
     
       4. The self-aligned field effect transistor structure of  claim 1 , wherein an unrevealed portion of the at least one of the plurality of fins forming the n-type field effect transistor region is doped with a boron type dopant. 
     
     
       5. The self-aligned field effect transistor structure of  claim 1 , further comprising at least one gate. 
     
     
       6. The self-aligned field effect transistor structure of  claim 1 , wherein the boron doped layer of the n-type field effect transistor region is conformally deposited on top of the plurality of fins. 
     
     
       7. The self-aligned field effect transistor structure of  claim 6 , wherein the boron doped layer of the n-type field effect transistor region is a layer that is deposited by chemical vapor deposition or atomic layer deposition. 
     
     
       8. The self-aligned field effect transistor structure of  claim 1 , wherein the phosphorous or arsenic doped layer of the p-type field effect transistor region is conformally deposited on top of the plurality of fins. 
     
     
       9. The self-aligned field effect transistor structure of  claim 8 , wherein the phosphorous or arsenic doped layer of the p-type field effect transistor region is a layer that is deposited by chemical vapor deposition or atomic layer deposition. 
     
     
       10. The self-aligned field effect transistor structure of  claim 1 , wherein the boron doped layer of the n-type field effect transistor region has a thickness of 1 nm to 10 nm. 
     
     
       11. The self-aligned field effect transistor structure of  claim 1 , wherein the phosphorous or arsenic doped layer has a thickness of 1 nm to 10 nm. 
     
     
       12. The self-aligned field effect transistor structure of  claim 1 , wherein the insulator material comprises a shallow trench isolation oxide. 
     
     
       13. The self-aligned field effect transistor structure of  claim 1 , wherein at least one of the plurality of fins is doped under a fin channel. 
     
     
       14. The self-aligned field effect transistor of  claim 5 , wherein the gate comprises a high-k dielectric layer. 
     
     
       15. The self-aligned field effect transistor of  claim 5 , wherein the gate comprises a gate metal region.