Inventor
SCHUSTER STANLEY EVERETT
15 patents
Patents
15 patentsUS6087225AJul 11, 2000
Method for dual gate oxide dual workfunction CMOS
IBM92 citations98
US5895487AApr 20, 1999
Integrated processing and L2 DRAM cache
IBM203 citations97
US5805494ASep 8, 1998
Trench capacitor structures
IBM44 citations95
US6981096B1Dec 27, 2005
Mapping and logic for combining L1 and L2 directories and/or arrays
IBM21 citations92
US6946869B2Sep 20, 2005
Method and structure for short range leakage control in pipelined circuits
IBM31 citations92
US6925549B2Aug 2, 2005
Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages
IBM27 citations91
US6182233B1Jan 30, 2001
Interlocked pipelined CMOS
IBM36 citations91
US6081872AJun 27, 2000
Cache reloading performance improvement through the use of early select techniques with and without pipelining
IBM28 citations91
US6057188AMay 2, 2000
Trench capacitor structures
IBM38 citations91
US5770969AJun 23, 1998
Controllable decoupling capacitor
IBM18 citations83
US4097753AJun 27, 1978
Comparator circuit for a C-2C A/D and D/A converter
IBM24 citations77
US6608771B2Aug 19, 2003
Low-power circuit structures and methods for content addressable memories and random access memories
IBM9 citations73
US6512397B1Jan 28, 2003
Circuit structures and methods for high-speed low-power select arbitration
IBM12 citations73
US4001601AJan 4, 1977
Two bit partitioning circuit for a dynamic, programmed logic array
IBM9 citations73
US5890215AMar 30, 1999
Electronic computer memory system having multiple width, high speed communication buffer
IBM0 citations41