Inventor

MOEHLMANN ULRICH

DE20 patents

⚠️ This page may combine multiple inventors who share the name “MOEHLMANN ULRICH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOEHLMANN ULRICH

NXP BV

Phase locked loop with reduced noise

Configurable built-in self-test for an all digital phase locked loop

All digital phase locked loop (ADPLL) with frequency locked loop

Circuit arrangement, in particular phase-locked loop, as well as corresponding method

Self-testing of a phase-locked loop using a pseudo-random noise

Phase locked loop with phase and frequency lock detection

Digital phase locked loops

All-digital phase-locked loop (ADPLL) with reduced settling time

System and method of controlling frequency of a digitally controlled oscillator with temperature compensation

Fractional-N ADPLL with reference dithering

Clock frequency monitoring for a phase-locked loop based design

Feedback system monitoring

Phase locked loop with lock detector

Radar system

Analog phase selection test system

Arrangement for generating a decoder clock signal

TRIDENT MICROSYSTEMS FAR EAST

Circuit arrangement and method for locking onto and/or processing data, in particular audio, T[ele]v[ision] and/or video data

PHILIPS CORP

Digital phase-locked loop

NXP USA INC

Duty cycle detector self-testing

MOEHLMANN ULRICH

Sigma delta modulator