Inventor

THOME GARY W

US49 patents

⚠️ This page may combine multiple inventors who share the name “THOME GARY W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THOME GARY W

COMPAQ COMPUTER CORP

Fully pipelined and highly concurrent memory controller

System for arbitrating access to memory with dynamic priority assignment

MPEG motion compensation using operand routing and performing add and divide in a single instruction

System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot

System and method for routing operands within partitions of a source register to partitions within a destination register

Computer bridge interfaces for accelerated graphics port and peripheral component interconnect devices

Memory controller having all DRAM address and control singals provided synchronously from a single device

System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation

Memory controller having flip-flops for synchronously generating DRAM address and control signals from a single chip

Burst data transfer to single cycle data transfer conversion and strobe signal conversion

Memory system with FIFO data input

Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control

Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle

Memory controller having precharge prediction based on processor and PCI bus cycles

Enhanced wavetable processing technique on a vector processor having operand routing and slot selectable operations

System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device

Memory controller having precharge prediction based on processor and PC bus cycles

Memory controller having precharge prediction based on processor and PCI bus cycles

Burst SRAMS for use with a high speed clock

Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control

Systempro emulation in a symmetric multiprocessing computer system

Method for determining speeds of memory modules

Computer system which overrides write protection status during execution in system management mode

Expansion bus type determination apparatus

Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot

Memory controller including write posting queues, bus read control logic, and a data contents counter

Programmable memory controller having two level look-up for memory timing parameter

Microprocessor cache memory way prediction based on the way of previous memory read

System for flushing first and second caches upon detection of a write operation to write protected areas

Memory controller that dynamically predicts page misses

Memory controller for use with write-back cache system and multiple bus masters coupled to multiple buses

System design to support either Pentium Pro processors, Pentium II processors, and future processor without having to replace the system board

Circuit for disabling an address masking control signal using OR gate when a microprocessor is in a system management mode

Enhanced adaptive filtering technique

Microprocessor cache memory way prediction based on the way of a previous memory read

Burst SRAMs for use with a high speed clock

Computer system including a first level write-back cache and a second level cache

Computer system which overrides write protection status during execution in system management mode

Apparatus for asserting an end of cycle signal to a processor bus in a computer system if a special cycle is detected on the processor bus without taking action on the special cycle

Line drawing using operand routing and operation selective multimedia extension unit

Lock signal extension and interruption apparatus

Circuit for masking a dirty status indication provided by a cache dirty memory under certain conditions so that a cache memory controller properly controls a cache tag memory

Noncacheable address random access memory

Circuit for disabling an address masking control signal when a microprocessor is in a system management mode

Computer system speed control using memory refresh counter

Circuit for disabling an address masking control signal when a microprocessor is in a system management mode

Auxiliary control signal decode using high performance address lines

ADVANCED MICRO DEVICES INC

Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values

HEWLETT PACKARD ENTPR DEV LP

Embedded image management