Inventor

MOSTAFAZADEH SHAHRAM

US52 patents

⚠️ This page may combine multiple inventors who share the name “MOSTAFAZADEH SHAHRAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOSTAFAZADEH SHAHRAM

NAT SEMICONDUCTOR CORP

Lead frame design for chip scale package

Lead frame chip scale package

Lead frame design for increased chip pinout

Plastic package with exposed die

Method for connecting packages of a stacked ball grid array structure

Ball grid array package with enhanced thermal and electrical characteristics and electronic device incorporating same

High density integrated circuit package assembly with a heatsink between stacked dies

Ball grid array package with lead frame

Techniques for wafer level molding of underfill encapsulant

Semiconductor component package assembly including an integral RF/EMI shield

Tape ball lead integrated circuit package

Apparatus and method of manufacturing a stackable package for a semiconductor device

Bumped integrated circuits for optical applications

Chip scale pin array

Method to encapsulate bumped integrated circuit to create chip scale package

Plastic package with exposed die and method of making same

Chip sized package

Thermal ball lead integrated package

Leadless microelectronic package and a method to maximize the die size in the package

Multichip packages with exposed dice

Microarray lead frame

Die with integral pedestal having insulated walls

Packaging of semiconductor device with a non-opaque cover

Chip scale pin array

Multichip packages with exposed dice

Lead frame design for chip scale package

Ball grid array with heat sink

Ultra-thin composite package for integrated circuits

High density integrated circuit assembly combining leadframe leads with conductive traces

Lead frame having layered conductive planes

High density integrated circuit assembly combining leadframe leads with conductive traces

Method and apparatus for forming an underfill adhesive layer

Flip chip optical semiconductor on a PCB

Packaging of a semiconductor device with a non-opaque cover

Lead frame chip scale package

Metallurgy for copper plated wafers

Integrated circuit device package having a support coating for improved reliability during temperature cycling

Micro surface mount die package and method

Apparatus and method for force mounting semiconductor packages to printed circuit boards

Die-level opto-electronic device and method of making same

Bumped integrated circuits for optical applications

Lead frame chip scale package

Apparatus and method for force mounting semiconductor packages to printed circuit boards

Substrate for semiconductor packaging

Lead frame chip scale package

Method and apparatus to enclose dice

Method for molding a bumped wafer

Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components

Self-aligning single point bonding tool

ADLER STEVEN J

Integration of structurally-stable isolated capacitive micromachined ultrasonic transducer (CMUT) array cells and array elements