Inventor
DWARKADAS SANDHYA
US14 patents
⚠️ This page may combine multiple inventors who share the name “DWARKADAS SANDHYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
UNIV ROCHESTER
4 patentsUS6684298B1Jan 27, 2004
Dynamic reconfigurable memory hierarchy
UNIV ROCHESTER63 citations94
US7089443B2Aug 8, 2006
Multiple clock domain microprocessor
UNIV ROCHESTER33 citations91
US6834328B2Dec 21, 2004
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
UNIV ROCHESTER12 citations80
USRE42213EMar 8, 2011
Dynamic reconfigurable memory hierarchy
UNIV ROCHESTER3 citations62
IBM
2 patentsDWARKADAS SANDHYA
2 patentsBALASUBRAMONIAN RAJEEV
2 patentsUS7490220B2Feb 10, 2009
Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals
BALASUBRAMONIAN RAJEEV40 citations90
US8103856B2Jan 24, 2012
Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration
BALASUBRAMONIAN RAJEEV9 citations82