Dynamic reconfigurable memory hierarchy

Abstract

A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.

1. A data cache for caching data in a computing device, the data cache operating at a plurality of levels in a memory hierarchy, the data cache comprising:
 a plurality of subarrays for storing the data, each of the plurality of subarrays being divided into a plurality of individually addressable ways, each of the plurality of ways being individually configurable to operate at one of the plurality of levels in the memory hierarchy;  
 a decoder for addressing the data in the subarrays;  
 a global wordline connecting the decoder to each of the plurality of subarrays; and  
 a local wordline connecting the global wordline to each of the of  plurality of ways in each of the plurality of subarrays.  
 
     
     
       2. The data cache of  claim 1 , wherein:
 each of the plurality of subarrays has an end closest to the decoder; and  
 in each of the plurality of subarrays, the local wordline branches from the global wordline at the end closest to the decoder.  
 
     
     
       3. The data cache of  claim 1 , wherein the global wordline comprises a first plurality of repeater switches to isolate the plurality of subarrays from one another. 
     
     
       4. The data cache of  claim 3 , wherein, in each of the plurality of subarrays, the local wordline comprises a second plurality of repeater switches to isolate the plurality of ways from one another. 
     
     
       5. The data cache of  claim 1 , further comprising means for selectively disabling the plurality of subarrays. 
     
     
       6. The data cache of  claim 5 , further comprising means for selectively disabling the plurality of ways in each of the plurality of subarrays. 
     
     
       7. The data cache of  claim 1 , wherein the plurality of levels comprise L 1  and L 2 . 
     
     
       8. The data cache of  claim 1 , wherein the plurality of levels comprise L 2  and L 3 . 
     
     
       9. The data cache of  claim 8 , further comprising an L 1  cache of fixed size. 
     
     
       10. A translation look-aside buffer for use in a computing device, the translation look-aside buffer comprising:
 a plurality of increments, each for storing virtual page numbers and associated physical page numbers, each of the plurality of increments having an input and an output;  
 an input bus connected to the inputs of the plurality of increments;  
 an output bus connected to the outputs of the plurality of increments; and  
 switches in the input and output buses to disconnect the plurality of increments selectively from the input and output buses to vary a size of the translation look-aside buffer.  
 
     
     
       11. The translation look-aside buffer of  claim 10 , wherein the plurality of increments are connected in parallel to the input and output buses. 
     
     
       12. The translation look-aside buffer of  claim 10 , wherein each of the plurality of increments comprises:
 a first memory for storing the virtual page numbers, the first memory having an input and an output; and  
 a second memory for storing the physical page numbers, the second memory having an input and an output;  
 and wherein: 
 the output of the first memory is connected to the input of the second memory;  
 the input of the first memory is the input of the increment; and  
 the output of the second memory is the output of the increment.  
 
 
     
     
       13. A data cache, comprising:
   a subarray configured to be partitioned into a plurality of individually addressable ways, wherein each of the plurality of individually addressable ways is configurable to operate at each of a plurality of levels in a memory hierarchy;        a global wordline configured to couple the subarray to other subarrays; and        a local wordline configured to couple the global wordline to one or more of the plurality of individually addressable ways.     
     
     
       14. The data cache of  claim 13 , wherein the local wordline is configured to branch from the global wordline at an end of the subarray closest to a decoder. 
     
     
       15. The data cache of  claim 13 , wherein the global wordline includes a first plurality of repeater switches to isolate the subarray from the other subarrays. 
     
     
       16. The data cache of  claim 15 , wherein the local wordline includes a second plurality of repeater switches to isolate one individually addressable way from other individually addressable ways. 
     
     
       17. The data cache of  claim 13 , further comprising means for selectively disabling the subarray. 
     
     
       18. The data cache of  claim 17 , further comprising means for selectively disabling the plurality of individually addressable ways. 
     
     
       19. The data cache of  claim 13 , wherein the plurality of levels include at least an L 1  and an L 2  level. 
     
     
       20. The data cache of  claim 13 , wherein the plurality of levels include at least an L 2  and an L 3  level. 
     
     
       21. The data cache of  claim 20 , wherein the plurality of levels further includes a fixed- size L 1  cache.   
     
     
       22. A translation look- aside buffer comprising:      a plurality of increments configured to store virtual page numbers and associated physical page numbers;        an input bus coupled to a plurality of inputs corresponding to the plurality of increments;        an output bus coupled to a plurality of outputs corresponding to the plurality of increments; and        a plurality of switches configured to selectively disconnect the plurality of increments from the input or output buses to vary a size of the translation look - aside buffer.     
     
     
       23. The translation look- aside buffer of    claim 22   , wherein the plurality of increments are connected in parallel to the input or output buses.   
     
     
       24. The translation look- aside buffer of    claim 22   , wherein one or more of the plurality of increments includes:      a first memory configured to store the virtual page numbers; and        a second memory configured to store the physical page numbers;        wherein an output of the first memory is connected to an input of the second memory;        wherein an input of the first memory includes the at least one input of the plurality of increments; and        wherein an output of the second memory includes the at least one output of the plurality of increments.     
     
     
       25. A cache, comprising:
   means for storing data in a subarray configured to be partitioned into a plurality of individually addressable ways, wherein each of the plurality of individually addressable ways is configurable to operate at each of a plurality of levels in a memory hierarchy;        means for electrically isolating the subarray from other subarrays; and        means for electrically isolating one individually addressable way from other individually addressable ways.     
     
     
       26. The cache of  claim 25 , wherein the means for electrically isolating each individually addressable way is configured to branch from the means for electrically isolating the subarray at an end of the subarray closest to a decoder. 
     
     
       27. The cache of  claim 25 , wherein the means for electrically isolating the subarray includes a first plurality of repeater switches to isolate the subarray from the other subarrays. 
     
     
       28. The cache of  claim 25 , wherein the means for electrically isolating the one individually addressable way includes a second plurality of repeater switches to isolate the one individually addressable way from the other individually addressable ways. 
     
     
       29. The cache of  claim 25 , further comprising means for selectively disabling the subarray. 
     
     
       30. The cache of  claim 25 , further comprising means for selectively disabling the plurality of individually addressable ways. 
     
     
       31. The cache of  claim 25 , wherein the plurality of levels include at least an L 1  and an L 2  level. 
     
     
       32. The cache of  claim 25 , wherein the plurality of levels include at least an L 2  and an L 3  level. 
     
     
       33. The cache of  claim 32 , wherein the plurality of levels further includes a fixed- size L 1  cache.   
     
     
       34. A translation look- aside buffer comprising:      means for storing virtual page numbers and associated physical page numbers;        means for coupling to at least one input of the means for storing;        means for coupling to at least one output of the means for storing; and        means for selectively disconnecting the means for storing from the means for coupling to at least one input or the means for coupling to at least one output to vary a size of the translation look - aside buffer;        wherein the means for storing includes:      a first memory means configured to store the virtual page numbers; and        a second memory means configured to store the physical page numbers;          wherein an output of the first memory means is connected to an input of the second memory means;        wherein an input of the first memory means includes the at least one input of the means for storing; and        wherein an output of the second memory means includes the at least one output of the means for storing.     
     
     
       35. The translation look- aside buffer of    claim 34   , wherein the means for storing connected in parallel to the means for coupling to at least one input or the means for coupling to at least one output.