Inventor

SLEIGHT JEFFREY W

US261 patents

⚠️ This page may combine multiple inventors who share the name “SLEIGHT JEFFREY W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SLEIGHT JEFFREY W

IBM

Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement

High-performance CMOS devices on hybrid crystal oriented substrates

Non-replacement gate nanomesh field effect transistor with pad regions

Nanowire mesh device and method of fabricating same

Nanowire mesh device and method of fabricating same

Maskless process for suspending and thinning nanowires

Selective floating body SRAM cell

Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain

III-V nanowire FET with compositionally-graded channel and wide-bandgap core

Diode structure and method for FINFET technologies

Non-replacement gate nanomesh field effect transistor with pad regions

Gate-all-around nanowire field effect transistors

Curved FINFETs

Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance

Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension

Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby

III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology

Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels

Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth

Wire-last gate-all-around nanowire FET

Epitaxial growth techniques for reducing nanowire dimension and pitch

Stacked planar double-gate lamellar field-effect transistor

Complementary metal-oxide silicon having silicon and silicon germanium channels

Tuning gate lengths in semiconductor device structures

CHANG JOSEPHINE B

Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices

Hybrid CMOS nanowire mesh device and FINFET device

Nanowire FET and finFET

Bulk FinFET and SOI FinFET hybrid technology

Multiple Vt field-effect transistor devices

Hybrid CMOS nanowire mesh device and PDSOI device

Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices

Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices

Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices

Double gate planar field effect transistors

Asymmetric finFET device with improved parasitic resistance and capacitance

Multiple Vt field-effect transistor devices

BANGSARUNTIP SARUNYA

Epitaxially thickened doped or undoped core nanowire FET structure and method for increasing effective device width

Replacement gate fin first wire last gate all around devices

Nanowire FET and finFET hybrid technology

Contacts for nanowire field effect transistors

Hybrid CMOS technology with nanowire devices and double gated planar devices

Planar and nanowire field effect transistors

Maskless process for suspending and thinning nanowires

Generation of multiple diameter nanowire field effect transistors

Nanowire tunnel field effect transistors

Nanowire circuits in matched devices

Gate-all-around nanowire tunnel field effect transistors

Self-aligned contacts for nanowire field effect transistors

GLOBALFOUNDRIES INC

Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitrides

Method and structure for III-V nanowire tunnel FETs