Inventor

ZHANG YANLI

US173 patents

⚠️ This page may combine multiple inventors who share the name “ZHANG YANLI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHANG YANLI

SANDISK TECHNOLOGIES LLC

Three-dimensional flat NAND memory device having curved memory elements and methods of making the same

Three-dimensional flat NAND memory device including concave word lines and method of making the same

Three-dimensional memory device with self-aligned multi-level drain select gate electrodes

Method of making a three-dimensional memory device using a multi-step hot phosphoric acid wet etch process

Three-dimensional memory device having a multilevel drain select gate electrode and method of making thereof

Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same

Three-dimensional memory device containing a lateral source contact and method of making the same

Memory hole size variation in a 3D stacked memory

Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making and using thereof

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

Ferroelectric memory device containing a series connected select gate transistor and method of forming the same

Ferroelectric memory device containing word lines and pass gates and method of forming the same

Ferroelectric memory device containing word lines and pass gates and method of forming the same

Three-dimensional memory device with self-aligned vertical conductive strips having a gate-all-around configuration and method of making the same

Three-dimensional memory device with logic signal routing through a memory die and methods of making the same

Three-dimensional flat NAND memory device having curved memory elements and methods of making the same

Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same

Three-dimensional memory device with thickened word lines in terrace region

Three-dimensional memory device having direct source contact and metal oxide blocking dielectric and method of making thereof

Three-dimensional memory device including partially surrounding select gates and fringe field assisted programming thereof

Three-dimensional memory device containing floating gate select transistor

Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof

High voltage field effect transistor with laterally extended gate dielectric and method of making thereof

Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of making thereof

Three-dimensional memory device having drain select level isolation structure and method of making thereof

Forming memory cell film in stack opening

Three-dimensional memory device with partially discrete charge storage regions and method of making thereof

Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same

Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof

Stacked vertical memory array architectures, systems and methods

SANDISK TECHNOLOGIES INC

Compact three dimensional vertical NAND and method of making thereof

Vertical NAND and method of making thereof using sequential stack etching and self-aligned landing pad

Three dimensional memory device with peripheral devices under dummy dielectric layer stack and method of making thereof

Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same

Three dimensional NAND devices with air gap or low-k core

Floating gate ultrahigh density vertical NAND flash memory

Monolithic three-dimensional NAND strings and methods of fabrication thereof

Three dimensional NAND device with channel contacting conductive source line and method of making thereof

3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same

Three dimensional NAND device containing dielectric pillars for a buried source line and method of making thereof

Monolithic three dimensional NAND strings and methods of fabrication thereof

Enhanced channel mobility three-dimensional memory structure and method of making thereof

Three-dimensional memory device with metal and silicide control gates

3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same

Three-dimensional memory structure having a back gate electrode

Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer

Three dimensional NAND device having nonlinear control gate electrodes and method of making thereof

Select gate transistor with single crystal silicon for three-dimensional memory

Operation modes for an inverted NAND architecture

ZHANG YANLI

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