Inventor

FAZAN PIERRE C

US142 patents

⚠️ This page may combine multiple inventors who share the name “FAZAN PIERRE C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FAZAN PIERRE C

MICRON TECHNOLOGY INC

Method of forming a Ta2 O5 dielectric layer, method of forming a capacitor having a Ta2 O5 dielectric layer, and capacitor construction

Uniform dielectric film deposition on textured surfaces

Sputter and CVD deposited titanium nitride barrier layer between a platinum layer and a polysilicon plug

Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a Ta2 O5 dielectric layer and amorphous diffusion barrier layer

Process for fabricating a cup-shaped DRAM capacitor using a multi-layer partly-sacrificial stack

Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Spacers used to form isolation trenches with improved corners

Process for creating fully-recessed field isolation regions by oxidizing a selectively-grown epitaxial silicon layer

Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography

Scalable high dielectric constant capacitor

Process for improving roughness of conductive layer

Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process

Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same

Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug

Method for forming a capacitor compatible with high dielectric constant materials having two independent insulative layers

Process for improving roughness of conductive layer

Processing methods of forming a capacitor, and capacitor construction

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a b. Ta.su2 O5 dielectric layer with amorphous diffusion barrier layer

Method of deposting uniform dielectric film deposition on textured surfaces

Method of forming integrated stacked capacitors with rounded corners

Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same

Isolation structure of a shallow semiconductor device trench

Method of fabricating a bottom electrode with rounded corners for an integrated memory cell capacitor

Spacers used to form isolation trenches with improved corners

High pressure reoxidation anneal of silicon nitride for reduced thermal budget silicon processing

Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path

Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor

Double DRAM cell

Method for forming low resistance DRAM digit-line

Double DRAM cell

Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers

Method of forming a capacitor having container members

DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance

Semiconductor memory circuitry

Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in an 8-inch wafer

Method of forming a thin film transistor

Method of forming a capacitor

Semiconductor memory circuitry including die sites for 16M to 17M memory cells in an 8″ wafer

Method of forming a capacitor

Method of forming a Ta2O5 dielectric layer, method of forming a capacitor having a Ta2O5 dielectric layer, and capacitor construction

Method of forming a thin film transistor

Method of trench isolation using spacers to form isolation trenches with protected corners

Method of reducing stress-induced defects in silicon

Method of selective texfturing for patterned polysilicon electrodes

Method of fabricating a gate having a barrier of titanium silicide

MICRON SEMICONDUCTOR INC

Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same

Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same

Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device