Semiconductor memory circuitry

Abstract

Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. An integrated circuit includes a semiconductor die, a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells. The memory cells are formed with a minimum capable photolithographic feature dimension. A single memory cell consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension.

1. An integrated circuit comprising:
 a semiconductor die; 
 a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, each of the plurality of memory cells including at least one container-configured capacitor having a storage node including a roughened outer surface in a substantially vertical dimension with respect to the semiconductor die for storing electrical charge to define a logic level, each of the plurality of memory cells coupling to a word line formed substantially below the at least one container-configured capacitor and each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor; and 
 circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells; 
 wherein the memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension. 
 
     
     
       2. The integrated circuit as claimed in  claim 1 , wherein the circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells includes column addressing circuitry for addressing columns of the memory cells, and sense amplifier circuitry for sensing signals from rows of the memory cells. 
     
     
       3. The integrated circuit as claimed in  claim 1 , wherein the single one of the memory cells consumes an area of no more than six times the square of the minimum capable photolithographic feature dimension. 
     
     
       4. The integrated circuit as claimed in  claim 1 , wherein the memory cells are dynamic random access memory cells. 
     
     
       5. The integrated circuit as claimed in  claim 1 , wherein at least 67,108,864 functional and operably addressable memory cells are formed on the semiconductor die. 
     
     
       6. The integrated circuit as claimed in  claim 1 , wherein at least 67,108,864 and no more than 68,000,000 functional and operably addressable memory cells are formed on the semiconductor die. 
     
     
       7. The integrated circuit as claimed in  claim 6 , wherein all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 53 mm 2 . 
     
     
       8. The integrated circuit as claimed in  claim 6 , wherein all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 40 mm 2 . 
     
     
       9. The integrated circuit as claimed in  claim 1 , wherein at least 16,777,216 functional and operably addressable memory cells are formed on the semiconductor die. 
     
     
       10. The integrated circuit as claimed in  claim 9 , wherein all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 14 mm 2 . 
     
     
       11. The integrated circuit as claimed in  claim 9 , wherein all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 11. 
     
     
       12. The integrated circuit as claimed in  claim 1 , wherein at least 4,194,394 functional and operably addressable memory cells are formed on the semiconductor die. 
     
     
       13. The integrated circuit as claimed in  claim 12 , wherein all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 3.3 mm 2 . 
     
     
       14. The integrated circuit as claimed in  claim 12 , wherein all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 2.5 mm 2 . 
     
     
       15. An integrated circuit comprising:
 a semiconductor die; 
 a plurality of functional and operably addressable dynamic random access memory cells arranged in at least one array formed on the semiconductor die, each of the plurality of memory cells including at least one container-configured capacitor having a storage node including a roughened outer surface in a substantially vertical dimension with respect to the semiconductor die for storing electrical charge to define a logic level, each of the plurality of memory cells coupling to a word line formed substantially below the at least one container-configured capacitor and each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor; 
 column addressing circuitry formed on the semiconductor die and coupled to the memory cells for addressing columns of the memory cells, and 
 sense amplifier circuitry formed on the semiconductor die and coupled to the memory cells for sensing signals from rows of the memory cells; 
 wherein the memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension. 
 
     
     
       16. The integrated circuit as claimed in  claim 15 , wherein at least 67,108,864 functional and operably addressable memory cells are formed on the semiconductor die. 
     
     
       17. The integrated circuit as claimed in  claim 15 , wherein at least 67,108,864 and no more than 68,000,000 functional and operably addressable memory cells are formed on the semiconductor die, and all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 53 mm 2 . 
     
     
       18. The integrated circuit as claimed in  claim 15 , wherein at least 16,777,216 functional and operably addressable memory cells are formed on the semiconductor die, and all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 14 mm 2 . 
     
     
       19. The integrated circuit as claimed in  claim 15 , wherein at least 4,194,394 functional and operably addressable memory cells are formed on the semiconductor die, and all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die which is no greater than 3.3 mm 2 . 
     
     
       20. An integrated circuit comprising:
 a semiconductor die; 
 a plurality of functional and operably addressable dynamic random access memory cells arranged in at least one array formed on the semiconductor die, each of the plurality of memory cells including at least one container-configured capacitor having a storage node including a roughened outer surface in a substantially vertical dimension with respect to the semiconductor die for storing electrical charge to define a logic level, each of the plurality of memory cells coupling to a word line formed substantially below the at least one container-configured capacitor and each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor; 
 column addressing circuitry formed on the semiconductor die and coupled to the memory cells for addressing columns of the memory cells, and 
 sense amplifier circuitry formed on the semiconductor die and coupled to the memory cells for sensing signals from rows of the memory cells; 
 wherein the memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than six times the square of the minimum capable photolithographic feature dimension. 
 
     
     
       21. The integrated circuit as claimed in  claim 20 , wherein at least 67,108,864 functional and operably addressable memory cells are formed on the semiconductor die. 
     
     
       22. The integrated circuit as claimed in  claim 20 , wherein at least 67,108,864 and no more than 68,000,000 functional and operably addressable memory cells are formed on the semiconductor die, and all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 53 mm 2 . 
     
     
       23. The integrated circuit as claimed in  claim 20 , wherein at least 16,777,216 functional and operably addressable memory cells are formed on the semiconductor die, and all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 14 mm 2 . 
     
     
       24. The integrated circuit as claimed in  claim 20 , wherein at least 4,194,394 functional and operably addressable memory cells are formed on the semiconductor die, and all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die which is no greater than 3.3 mm 2 . 
     
     
       25. A plurality of integrated circuits comprising:
 a processed semiconductor wafer ready for dicing; and 
 a plurality of die sites on the processed semiconductor wafer; 
 wherein a predominant number of a total number of die sites on the processed semiconductor wafer include a plurality of functional and operably addressable memory cells arranged in at least one array, each of the plurality of memory cells including at least one container-configured capacitor having a storage node including a roughened outer surface in a substantially vertical dimension with respect to the semiconductor wafer for storing electrical charge to define a logic level, each of the plurality of memory cells coupling to a word line formed substantially below the at least one container-configured capacitor and each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor, and circuitry coupled to the memory cells for permitting data to be written to and read from the memory cells, wherein the memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension. 
 
     
     
       26. The plurality of integrated circuits as claimed in  claim 25 , wherein the circuitry coupled to the memory cells for permitting data to be written to and read from the memory cells includes column addressing circuitry for addressing columns of the memory cells, and sense amplifier circuitry for sensing signals from rows of the memory cells. 
     
     
       27. The plurality of integrated circuits as claimed in  claim 25 , wherein the single one of the memory cells consumes an area of no more than six times the square of the minimum capable photolithographic feature dimension. 
     
     
       28. The plurality of integrated circuits as claimed in  claim 25 , wherein the memory cells are dynamic random access memory cells. 
     
     
       29. The plurality of integrated circuits as claimed in  claim 25 , wherein the predominant number of the total number of die sites on the processed semiconductor wafer include at least 256,000,000 functional and operably addressable memory cells. 
     
     
       30. The plurality of integrated circuits as claimed in  claim 25 , wherein the predominant number of the total number of die sites on the processed semiconductor wafer include at least 256,000,000 and no more than 275,000,000 functional and operably addressable memory cells. 
     
     
       31. The plurality of integrated circuits as claimed in  claim 30 , wherein the processed semiconductor wafer has a major diameter of about 12 inches, and the total number of the die sites on the processed semiconductor wafer is at least 210. 
     
     
       32. The plurality of integrated circuits as claimed in  claim 30 , wherein the processed semiconductor wafer has a major diameter of about 8 inches, and the total number of the die sites on the processed semiconductor wafer is at least 86. 
     
     
       33. The plurality of integrated circuits as claimed in  claim 30 , wherein the processed semiconductor wafer has a major diameter of about 6 inches, and the total number of the die sites on the processed semiconductor wafer is at least 45. 
     
     
       34. The plurality of integrated circuits as claimed in  claim 25 , wherein the predominant number of the total number of die sites on the processed semiconductor wafer include at least 64,000,000 functional and operably addressable memory cells. 
     
     
       35. The plurality of integrated circuits as claimed in  claim 34 , wherein the processed semiconductor wafer has a major diameter of about 12 inches, and the total number of the die sites on the processed semiconductor wafer is at least 525. 
     
     
       36. The plurality of integrated circuits as claimed in  claim 34 , wherein the processed semiconductor wafer has a major diameter of about 8 inches, and the total number of the die sites on the processed semiconductor wafer is at least 200. 
     
     
       37. The plurality of integrated circuits as claimed in  claim 34 , wherein the processed semiconductor wafer has a major diameter of about 6 inches, and the total number of the die sites on the processed semiconductor wafer is at least 100. 
     
     
       38. The plurality of integrated circuits as claimed in  claim 25 , wherein the predominant number of the total number of die sites on the processed semiconductor wafer include at least 16,000,000 functional and operably addressable memory cells. 
     
     
       39. The plurality of integrated circuits as claimed in  claim 38 , wherein the processed semiconductor wafer has a major diameter of about 12 inches, and the total number of the die sites on the processed semiconductor wafer is at least 1780. 
     
     
       40. The plurality of integrated circuits as claimed in  claim 38 , wherein the processed semiconductor wafer has a major diameter of about 8 inches, and the total number of the die sites on the processed semiconductor wafer is at least 700. 
     
     
       41. The plurality of integrated circuits as claimed in  claim 38 , wherein the processed semiconductor wafer has a major diameter of about 6 inches, and the total number of the die sites on the processed semiconductor wafer is at least 375. 
     
     
       42. The plurality of integrated circuits as claimed in  claim 25 , wherein the predominant number of the total number of die sites on the processed semiconductor wafer include at least 4,000,000 functional and operably addressable memory cells. 
     
     
       43. The plurality of integrated circuits as claimed in  claim 42 , wherein the processed semiconductor wafer has a major diameter of about 12 inches, and the total number of the die sites on the processed semiconductor wafer is at least 5,975. 
     
     
       44. The plurality of integrated circuits as claimed in  claim 42 , wherein the processed semiconductor wafer has a major diameter of about 8 inches, and the total number of the die sites on the processed semiconductor wafer is at least 2,500. 
     
     
       45. The plurality of integrated circuits as claimed in  claim 42 , wherein the processed semiconductor wafer has a major diameter of about 6 inches, and the total number of the die sites on the processed semiconductor wafer is at least 1,300. 
     
     
       46. A plurality of integrated circuits comprising:
 a processed semiconductor wafer ready for dicing; and 
 a plurality of die sites on the processed semiconductor wafer; 
 wherein a predominant number of the total number of die sites on the processed semiconductor wafer include a plurality of functional and operably addressable dynamic random access memory cells arranged in at least one array, each of the plurality of memory cells including at least one container-configured capacitor having a storage node including a roughened outer surface in a substantially vertical dimension with respect to the semiconductor wafer for storing electrical charge to define a logic level, each of the plurality of memory cells coupling to a word line formed substantially below the at least one container-configured capacitor and each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor, column addressing circuitry coupled to the memory cells for addressing columns of the memory cells, sense amplifier circuitry coupled to the memory cells for sensing signals from rows of the memory cells, the memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension. 
 
     
     
       47. The plurality of integrated circuits as claimed in  claim 46 , wherein the single one of the memory cells consumes an area of no more than six times the square of the minimum capable photolithographic feature dimension. 
     
     
       48. The plurality of integrated circuits as claimed in  claim 46 , wherein the predominant number of the total number of die sites on the processed semiconductor wafer include at least 256,000,000 functional and operably addressable memory cells. 
     
     
       49. The plurality of integrated circuits as claimed in  claim 46 , wherein the predominant number of the total number of die sites on the processed semiconductor wafer include at least 256,000,000 and no more than 275,000,000 functional and operably addressable memory cells. 
     
     
       50. The plurality of integrated circuits as claimed in  claim 46 , wherein the predominant number of the total number of die sites on the processed semiconductor wafer include at least 64,000,000 functional and operably addressable memory cells. 
     
     
       51. The plurality of integrated circuits as claimed in  claim 46  wherein the predominant number of the total number of die sites on the processed semiconductor wafer include at least 16,000,000 functional and operably addressable memory cells. 
     
     
       52. The plurality of integrated circuits as claimed in  claim 46 , wherein the predominant number of the total number of die sites on the processed semiconductor wafer include at least 4,000,000 functional and operably addressable memory cells.