Inventor

MURTHY ANAND S

US242 patents

⚠️ This page may combine multiple inventors who share the name “MURTHY ANAND S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MURTHY ANAND S

INTEL CORP

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Semiconductor transistor having a backfilled channel material

Method for forming an integrated circuit

Epitaxially deposited source/drain

Method of making a semiconductor transistor

Transistor with improved tip profile and method of manufacture thereof

Field effect transistor structure with abrupt source/drain junctions

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Methods of making field effect transistor structure with partially isolated source/drain junctions

Nanowire transistor devices and forming techniques

Integration methods to fabricate internal spacers for nanowire devices

Selective germanium P-contact metalization through trench

Transistors with high concentration of boron doped germanium

Contact resistance reduction employing germanium overlayer pre-contact metalization

Selective germanium P-contact metalization through trench

Method of forming abrupt source drain metal gate transistors

Method of forming an element of a microelectronic circuit

Transistor with improved tip profile and method of manufacture thereof

Method of making a semiconductor transistor

Backside contact resistance reduction for semiconductor devices with metallization on both sides

Source/drain diffusion barrier for germanium NMOS transistors

Transistors with high concentration of germanium

Contact resistance reduction employing germanium overlayer pre-contact metalization

Contact resistance reduction employing germanium overlayer pre-contact metalization

Indium-rich NMOS transistor channels

High-mobility semiconductor source/drain spacer

High mobility strained channels for fin-based NMOS transistors

Techniques for achieving multiple transistor fin dimensions on a single die

CMOS nanowire structure

Nanowire transistor devices and forming techniques

Self-aligned contact metallization for reduced contact resistance

Pre-sculpting of Si fin elements prior to cladding for transistor channel applications

Transistor fabrication technique including sacrificial protective layer for source/drain at contact location

III-V layers for N-type and P-type MOS source-drain contacts

GLASS GLENN A

Selective germanium P-contact metalization through trench

Self-aligned 3-D epitaxial structures for MOS device fabrication

III-V layers for N-type and P-type MOS source-drain contacts

Nanowire transistor devices and forming techniques

Contact resistance reduction employing germanium overlayer pre-contact metalization

Column IV transistors for PMOS integration

Self-aligned contact metallization for reduced contact resistance

Contact resistance reduced P-MOS transistors employing Ge-rich contact layer

KIM SEIYON

Integration methods to fabricate internal spacers for nanowire devices

CMOS nanowire structure

CMOS nanowire structure

MURTHY ANAND S

Transistors with high concentration of boron doped germanium

Semiconductor device having doped epitaxial region and its methods of fabrication

CEA STEPHEN M

High mobility strained channels for fin-based transistors

CAPPELLANI ANNALISA

Multi-gate semiconductor device with self-aligned epitaxial source and drain