Inventor

GLASS GLENN A

US154 patents

⚠️ This page may combine multiple inventors who share the name “GLASS GLENN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GLASS GLENN A

INTEL CORP

Method for improving transistor performance through reducing the salicide interface resistance

Method for forming an integrated circuit

CMOS transistor junction regions formed by a CVD etching and deposition sequence

Method for improving transistor performance through reducing the salicide interface resistance

Nanowire transistor devices and forming techniques

Selective germanium P-contact metalization through trench

Transistors with high concentration of boron doped germanium

Contact resistance reduction employing germanium overlayer pre-contact metalization

Conversion of strain-inducing buffer to electrical insulator

Selective germanium P-contact metalization through trench

CMOS transistor junction regions formed by a CVD etching and deposition sequence

Selective deposition to improve selectivity and structures formed thereby

Methods for selective deposition to improve selectivity

Backside contact resistance reduction for semiconductor devices with metallization on both sides

Source/drain diffusion barrier for germanium NMOS transistors

Transistors with high concentration of germanium

Contact resistance reduction employing germanium overlayer pre-contact metalization

Contact resistance reduction employing germanium overlayer pre-contact metalization

Indium-rich NMOS transistor channels

High-mobility semiconductor source/drain spacer

High mobility strained channels for fin-based NMOS transistors

Techniques for achieving multiple transistor fin dimensions on a single die

CMOS nanowire structure

Nanowire transistor devices and forming techniques

Self-aligned contact metallization for reduced contact resistance

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition

Pre-sculpting of Si fin elements prior to cladding for transistor channel applications

Transistor fabrication technique including sacrificial protective layer for source/drain at contact location

III-V layers for N-type and P-type MOS source-drain contacts

Self-aligned contact metallization for reduced contact resistance

High mobility strained channels for fin-based transistors

Techniques for integration of Ge-rich p-MOS source/drain contacts

Tin doped III-V material contacts

Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer

GLASS GLENN A

Selective germanium P-contact metalization through trench

Self-aligned 3-D epitaxial structures for MOS device fabrication

III-V layers for N-type and P-type MOS source-drain contacts

Nanowire transistor devices and forming techniques

Contact resistance reduction employing germanium overlayer pre-contact metalization

Column IV transistors for PMOS integration

Self-aligned contact metallization for reduced contact resistance

Contact resistance reduced P-MOS transistors employing Ge-rich contact layer

Conversion of thin transistor elements from silicon to silicon germanium

KIM SEIYON

CMOS nanowire structure

CMOS nanowire structure

MURTHY ANAND S

Transistors with high concentration of boron doped germanium

CEA STEPHEN M

High mobility strained channels for fin-based transistors

CAPPELLANI ANNALISA

Conversion of strain-inducing buffer to electrical insulator

MOTOROLA INC

Quantum random address memory with nano-diode mixer

DAEDALUS PRIME LLC

Column IV transistors for PMOS integration