Inventor

CHRISTENSEN TODD ALAN

US54 patents

⚠️ This page may combine multiple inventors who share the name “CHRISTENSEN TODD ALAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHRISTENSEN TODD ALAN

IBM

Ring oscillator circuit for EDRAM/DRAM performance monitoring

Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices

Buried patterned conductor planes for semiconductor-on-insulator integrated circuit

Method for implementing SOI transistor source connections using buried dual rail distribution

Integrated circuit having integral decoupling capacitor

Multi-threaded cell for a memory

Method and ring oscillator for evaluating dynamic circuits

Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices

Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices

Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors

Implementing contacts for bodies of semiconductor-on-insulator transistors

Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors

Lower power and reduced device split local and continuous bitline for domino read SRAMs

Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distribution

Split local and continuous bitline for fast domino read SRAM

Bulk silicon voltage plane for SOI applications

Method for implementing domino SRAM leakage current reduction

Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test

Implementing tamper evident and resistant detection through modulation of capacitance

Method for improved power distribution in a three dimensional vertical integrated circuit

Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips

Method and circuit for implementing enhanced SRAM write and read performance ring oscillator

Implementing enhanced SRAM read performance sort ring oscillator (PSRO)

Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO)

Split local and continuous bitline requiring fewer wires

Implementing boosted wordline voltage in memories

Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usage

Method for implementing level shifter circuits for integrated circuits

Method and sum addressed cell encoder for enhanced compare and search timing for CAM compare

Apparatus for implementing domino SRAM leakage current reduction

Laser fuseblow protection method for silicon on insulator (SOI) transistors

Laser fuseblow protection method for silicon on insulator (SOI) transistors

High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus

Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under test

Implementing enhanced LBIST testing of paths including arrays

Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme

Apparatus for improved power distribution in a three dimensional vertical integrated circuit

Implementing enhanced dual mode SRAM performance screen ring oscillator

Semiconductor scheme for reduced circuit area in a simplified process

Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic

Array redundancy supporting multiple independent repairs

Semiconductor scheme for reduced circuit area in a simplified process

CHRISTENSEN TODD ALAN

Implementing physically unclonable function (PUF) utilizing EDRAM memory cell capacitance variation

Power distribution in a vertically integrated circuit

Vertical stacking of field effect transistor structures for logic gates

Vertical stacking of field effect transistor structures for logic gates

BEHRENDS DERICK GARDNER

Delay chain burn-in for increased repeatability of physically unclonable functions

Data security for dynamic random access memory using body bias to clear data at power-up

(unassigned)

Integrated circuit having integral decoupling capacitor

ALLEN DAVID HOWARD

Enhanced field effect transistor