Inventor

SIVAKUMAR SWAMINATHAN

US71 patents

⚠️ This page may combine multiple inventors who share the name “SIVAKUMAR SWAMINATHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SIVAKUMAR SWAMINATHAN

INTEL CORP

Imageable bottom anti-reflective coating for high resolution lithography

Method of controlling etch bias with a fixed lithography pattern for sub-micron critical dimension shallow trench applications

Advanced lithography and self-assembled devices

Dense memory arrays utilizing access transistors with back-side contacts

Patterning of vertical nanowire transistor channel and gate with directed self assembly

Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects

Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects

Pattern decomposition lithography techniques

Negative tone double patterning method

Double patterning techniques and structures

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

Advanced lithography and self-assembled devices

Forming self-aligned nano-electrodes

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

Advanced lithography and self-assembled devices

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

Advanced lithography and self-assembled devices

Fin shaping using templates and integrated circuit structures resulting therefrom

Three-dimensional memory arrays with layer selector transistors

Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects

Pattern decomposition lithography techniques

Pattern decomposition lithography techniques

Solvent vapor-assisted plasticization of photoresist films to achieve critical dimension reduction during temperature reflow

Die interconnection scheme for providing a high yielding process for high performance microprocessors

Cooling approaches for stitched dies

Gate-all-around integrated circuit structures having oxide sub-fins

Gate aligned contact and method to fabricate same

Gate aligned contact and method to fabricate same

FIN shaping using templates and integrated circuit structures resulting therefrom

Gate-all-around integrated circuit structures having oxide sub-fins

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures

Gate aligned contact and method to fabricate same

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures

Gate aligned contact and method to fabricate same

Patterning of vertical nanowire transistor channel and gate with directed self assembly

Patterning of vertical nanowire transistor channel and gate with directed self assembly

Common plate capacitor array connections, and processes of making same

Imageable bottom anti-reflective coating for high resolution lithography

Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material

Three-dimensional memory arrays with layer selector transistors

Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material

Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging

Pattern decomposition lithography techniques

Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby

Non-collinear end-to-end structures with sub-resolution assist features

GOLONZKA OLEG

Gate aligned contact and method to fabricate same

WANG YIH

6F2 DRAM cell

NYHUS PAUL A

Patterning of vertical nanowire transistor channel and gate with directed self assembly

WALLACE CHARLES H

Pattern decomposition lithography techniques

SIVAKUMAR SWAMINATHAN

Spacer assisted pitch division lithography