Inventor
MAURY ALVARO
US26 patents
⚠️ This page may combine multiple inventors who share the name “MAURY ALVARO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LUCENT TECHNOLOGIES INC
10 patentsUS6033293AMar 7, 2000
Apparatus for performing chemical-mechanical polishing
LUCENT TECHNOLOGIES INC140 citations97
US6261958B1Jul 17, 2001
Method for performing chemical-mechanical polishing
LUCENT TECHNOLOGIES INC44 citations95
US6008123ADec 28, 1999
Method for using a hardmask to form an opening in a semiconductor substrate
LUCENT TECHNOLOGIES INC77 citations95
US6146975ANov 14, 2000
Shallow trench isolation
LUCENT TECHNOLOGIES INC40 citations91
US6110012AAug 29, 2000
Chemical-mechanical polishing apparatus and method
LUCENT TECHNOLOGIES INC34 citations91
US6051500AApr 18, 2000
Device and method for polishing a semiconductor substrate
LUCENT TECHNOLOGIES INC35 citations89
US6624039B1Sep 23, 2003
Alignment mark having a protective oxide layer for use with shallow trench isolation
LUCENT TECHNOLOGIES INC21 citations88
US6110831AAug 29, 2000
Method of mechanical polishing
LUCENT TECHNOLOGIES INC17 citations79
US6287173B1Sep 11, 2001
Longer lifetime warm-up wafers for polishing systems
LUCENT TECHNOLOGIES INC5 citations62
US6217419B1Apr 17, 2001
Chemical-mechanical polisher
LUCENT TECHNOLOGIES INC1 citations52
AGERE SYST GUARDIAN CORP
6 patentsUS6372605B1Apr 16, 2002
Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing
AGERE SYST GUARDIAN CORP54 citations94
US6368972B1Apr 9, 2002
Method for making an integrated circuit including alignment marks
AGERE SYST GUARDIAN CORP23 citations90
US6274933B1Aug 14, 2001
Integrated circuit device having a planar interlevel dielectric layer
AGERE SYST GUARDIAN CORP18 citations80
US6309900B1Oct 30, 2001
Test structures for testing planarization systems and methods for using same
AGERE SYST GUARDIAN CORP14 citations73
US6354910B1Mar 12, 2002
Apparatus and method for in-situ measurement of polishing pad thickness loss
AGERE SYST GUARDIAN CORP11 citations70
US6281128B1Aug 28, 2001
Wafer carrier modification for reduced extraction force
AGERE SYST GUARDIAN CORP3 citations59
AGERE SYSTEMS INC
4 patentsUS6910907B2Jun 28, 2005
Contact for use in an integrated circuit and a method of manufacture therefor
AGERE SYSTEMS INC115 citations98
US7005724B2Feb 28, 2006
Semiconductor device and a method of manufacture therefor
AGERE SYSTEMS INC5 citations73
US6548906B2Apr 15, 2003
Method for reducing a metal seam in an interconnect structure and a device manufactured thereby
AGERE SYSTEMS INC2 citations63
US7811944B2Oct 12, 2010
Semiconductor device and a method of manufacture therefor
AGERE SYSTEMS INC1 citations51
CHARTERED SEMICONDUCTOR MFG
3 patentsUS6984166B2Jan 10, 2006
Zone polishing using variable slurry solid content
CHARTERED SEMICONDUCTOR MFG35 citations89
US6821886B1Nov 23, 2004
IMP TiN barrier metal process
CHARTERED SEMICONDUCTOR MFG19 citations82
US7163438B2Jan 16, 2007
Zone polishing using variable slurry solid content
CHARTERED SEMICONDUCTOR MFG2 citations59