Inventor

CHOW SENG GUAN

SG207 patents

⚠️ This page may combine multiple inventors who share the name “CHOW SENG GUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOW SENG GUAN

STATS CHIPPAC LTD

Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die

Method of forming stress relief layer between die and interconnect structure

Method of mounting an integrated circuit package in an encapsulant cavity

Embedded semiconductor die package and method of making the same using metal frame carrier

Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant

Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors

Semiconductor device and method of forming the device using sacrificial carrier

Integrated circuit package system for electromagnetic isolation

Integrated circuit package system with die and package combination

Method of making a wafer level integration package

Method of fabricating a 3-D package stacking system

Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides

Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides

Pre-molded leadframe and method therefor

Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer

Embedded semiconductor die package and method of making the same using metal frame carrier

Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer

Package-on-package using through-hole via die on saw streets

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die

Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant

Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP

Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant

Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof

Integrated circuit package-in-package system with wire-in-film encapsulant

Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof

Integrated circuit package system with an encapsulant cavity and method of fabrication thereof

Wafer level integration package

Leadframe package for MEMS microphone assembly

Multi-chip package system

Same size die stacked package having through-hole vias formed in organic material

ST ASSEMBLY TEST SERVICES LTD

Stacked semiconductor packages and method for the fabrication thereof

Stacked semiconductor packages

Semiconductor package with passive device integration

Super thin/super thermal ball grid array package

Semiconductor package having heat sink attached to pre-molded cavities and method for creating the package

Heat spreaders, heat spreader packages, and fabrication methods for use with flip chip semiconductor devices

CHOW SENG GUAN

Integrated circuit package system with internal stacking module

Integrated circuit package system with penetrable film adhesive

Integrated circuit package system with interposer

Bridge stack integrated circuit package-on-package system

SHIM IL KWON

Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die

Integrated circuit package-on-package stacking system and method of manufacture thereof

Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer

HUANG RUI

Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure

Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors

ST ASSEMBLY TEST SERVICE LTD

PBGA substrate for anchoring heat sink

CHO NAMJU

Integrated circuit packaging system with stacking interconnect and method of manufacture thereof

LIN YAOJIAN

Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief

PENDSE RAJENDRA D

Integrated circuit package system for package stacking and method of manufacture therefor