Inventor

LIM SEOW-FONG

US38 patents

⚠️ This page may combine multiple inventors who share the name “LIM SEOW-FONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIM SEOW-FONG

WINBOND ELECTRONICS CORP

Resistive random access memory apparatus with forward and reverse reading modes

Physical unclonable function code generating method and providing apparatus thereof

RRAM with plurality of 1TnR structures

NVFF monotonic counter and method of implementing same

Non-volatile semiconductor memory device

Physical unclonable function code generation apparatus and method thereof

Memory device and control method thereof

Apparatus for providing adjustable reference voltage for sensing read-out data for memory

Resistive memory apparatus and method for writing data thereof

Write method for resistive memory

Resistive memory

Memory storage apparatus with dynamic data repair mechanism and method of dynamic data repair thereof

Memory apparatus having hierarchical error correction code layer

Operating method of resistive memory element

Non-volatile memory and reset method thereof

Memory device and multi physical cells error correction method thereof

Memory apparatus and data accessing method thereof

Encoding method and memory storage apparatus using the same

Encoding method and a memory storage apparatus using the same

Non-volatile memory and erase controlling method thereof

Programmable array logic circuit and operating method thereof

UNITY SEMICONDUCTOR CORP

Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross point arrays

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

SIAU CHANG HUA

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

CHEVALLIER CHRISTOPHE J

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

NANJING UCUN TECH INC

Two-bit memory cell and circuit structure calculated in memory thereof

LIN CHI-SHUN

Reference cell circuit and method of producing a reference current