Non-volatile memory and reset method thereof

Abstract

A non-volatile memory and a reset method thereof are provided. The reset method includes: performing a first reset operation on a plurality of memory cells; recording a plurality of first verifying currents respectively corresponding to a plurality of first failure memory cells; performing a second reset operation on the first failure memory cells, and verifying second failure memory cells to obtain a plurality of second verifying currents; setting a first voltage modify flag according to a plurality of first ratios between the first verifying currents and the respectively corresponding second verifying currents; and adjusting a reset voltage for performing the first reset operation and the second reset operation according to the first voltage modify flag.

What is claimed is: 
     
       1. A reset method of non-volatile memory, comprising:
 performing a first reset operation on a plurality of memory cells; 
 recording a plurality of first verifying currents respectively corresponding to a plurality of first failure memory cells; 
 performing a second reset operation on the first failure memory cells, and verifying a plurality of second failure memory cells to obtain a plurality of second verifying currents; 
 setting a first voltage modify flag according to a plurality of first ratios between the second verifying currents and the respectively corresponding first verifying currents; and 
 adjusting a reset voltage for performing the first reset operation and the second reset operation according to the first voltage modify flag. 
 
     
     
       2. The reset method of  claim 1 , wherein a step of setting the first voltage modify flag according to the first ratios between the second verifying currents and the respectively corresponding first verifying currents comprises:
 determining whether each of the first ratios is greater than a preset value; and 
 setting the first voltage modify flag when at least one of the first ratios is greater than the preset value. 
 
     
     
       3. The reset method of  claim 1 , further comprising:
 performing a third reset operation on the second failure memory cells, and verifying a plurality of third failure memory cells to obtain a plurality of third verifying currents; 
 setting a second voltage modify flag according to a plurality of second ratios between the third verifying currents and the respectively corresponding second verifying currents; and 
 adjusting the reset voltage according to the first voltage modify flag and the second voltage modify flag. 
 
     
     
       4. The reset method of  claim 3 , wherein a step of setting the second voltage modify flag according to the second ratios between the third verifying currents and the respectively corresponding second verifying currents comprises:
 determining whether each of the second ratios is greater than a preset value; and 
 setting the second voltage modify flag when at least one of the second ratios is greater than the preset value. 
 
     
     
       5. The reset method of  claim 3 , further comprising:
 counting a first fail bit count of the third failure memory cells verified as a reset failure after the third reset operation; and 
 adjusting the second voltage modify flag according to the first fail bit count. 
 
     
     
       6. The reset method of  claim 5 , wherein a step of adjusting the second voltage modify flag according to the first fail bit count comprises:
 setting the second voltage modify flag when the fail bit count is greater than a threshold. 
 
     
     
       7. The reset method of  claim 5 , further comprising:
 performing a fourth reset operation on the third failure memory cells verified as the reset failure after the third reset operation, and verifying a plurality of fourth failure memory cells to obtain a plurality of fourth verifying currents; 
 setting a third voltage modify flag according to a ratio between each of the fourth verifying currents and each of the third verifying currents; and 
 adjusting the reset voltage according to the first voltage modify flag, the second voltage modify flag and the third voltage modify flag, wherein the first voltage modify flag, the second voltage modify flag and the third voltage modify flag may be identical or different. 
 
     
     
       8. The reset method of  claim 7 , when the first voltage modify flag, the second voltage modify flag and the third voltage modify flag are different, the reset method further comprising:
 providing a plurality of memory cells for respectively storing the first voltage modify flag, the second voltage modify flag and the third voltage modify flag; or 
 providing a multi-bit data memory cell for storing the first voltage modify flag, the second voltage modify flag and the third voltage modify flag. 
 
     
     
       9. The reset method of  claim 7 , wherein a step of setting the third voltage modify flag according to the ratio between each of the fourth verifying currents and each of the third verifying currents comprises:
 setting the third voltage modify flag when the fail bit count is greater than a threshold. 
 
     
     
       10. The reset method of  claim 7 , further comprising:
 counting a second fail bit count of the fourth failure memory cells verified as the reset failure after the fourth reset operation; and 
 comparing the second fail bit count with a maximum correcting count of an error correcting operation to generate a comparison result, and performing an error bit correcting operation or ending a reset operation according to the comparison result. 
 
     
     
       11. The reset method of  claim 10 , wherein a step of comparing the second fail bit count with the maximum correcting count of the error correcting operation to generate the comparison result, and performing the error bit correcting operation or ending the reset operation according to the comparison result comprises:
 ending the reset operation when the second fail bit count is greater than the maximum correcting count; and 
 performing the error correcting operation when the second fail bit count is not greater than the maximum correcting count. 
 
     
     
       12. A non-volatile memory, comprising:
 a memory cell array; and 
 a controller, coupled to the memory cell array, and configured for:
 performing a first reset operation on a plurality of memory cells; 
 recording a plurality of first verifying currents respectively corresponding to the first failure memory cells; 
 performing a second reset operation on the first failure memory cells, and verifying a plurality of second failure memory cells to obtain a plurality of second verifying currents; 
 setting a first voltage modify flag according to a plurality of first ratios between the second verifying currents and the respectively corresponding first verifying currents; and 
 adjusting a reset voltage for performing the first reset operation and the second reset operation according to the first voltage modify flag. 
 
 
     
     
       13. The non-volatile memory of  claim 12 , further comprising:
 an operator, coupled to the controller and the memory cell array, and configured for calculating a ratio between each of the second verifying currents and each of the first verifying currents. 
 
     
     
       14. The non-volatile memory of  claim 12 , wherein the controller is further configured for:
 determining whether each of the first ratios is greater than a preset value; and 
 setting the first voltage modify flag when at least one of the first ratios is greater than the preset value. 
 
     
     
       15. The non-volatile memory of  claim 12 , wherein the controller is further configured for:
 performing a third reset operation on the second failure memory cells verified as a reset failure after the second reset operation, and verifying a plurality of third failure memory cells to obtain a plurality of third verifying currents; 
 setting a second voltage modify flag according to a plurality of second ratios between the third verifying currents and the respectively corresponding second verifying currents; and 
 adjusting the reset voltage according to the first voltage modify flag and the second voltage modify flag. 
 
     
     
       16. The non-volatile memory of  claim 15 , wherein the controller is further configured for:
 determining whether each of the second ratios is greater than a preset value; and 
 setting the second voltage modify flag when at least one of the second ratios is greater than the threshold. 
 
     
     
       17. The non-volatile memory of  claim 15 , further comprising:
 a counter, configured for counting a first fail bit count of the third failure memory cells verified as the reset failure after the third reset operation, and 
 the controller is further configured for:
 adjusting the second voltage modify flag according to the first fail bit count. 
 
 
     
     
       18. The non-volatile memory of  claim 17 , wherein the controller is further configured for:
 performing a fourth reset operation on a plurality of third failure memory cells verified as the reset failure after the third reset operation, and verifying a plurality of fourth failure memory cells to obtain a plurality of fourth verifying currents; 
 setting a third voltage modify flag according to a ratio between each of the fourth verifying currents and each of the third verifying currents; and 
 adjusting the reset voltage according to the first voltage modify flag, the second voltage modify flag and the third voltage modify flag, wherein the first voltage modify flag, the second voltage modify flag and the third voltage modify flag may be identical or different. 
 
     
     
       19. The non-volatile memory of  claim 18 , wherein when the first voltage modify flag, the second voltage modify flag and the third voltage modify flag are different, the first voltage modify flag, the second voltage modify flag and the third voltage modify flag are respectively stored in a plurality of memory cells, or the first voltage modify flag, the second voltage modify flag and the third voltage modify flag are stored together in a multi-bit data memory cell. 
     
     
       20. The non-volatile memory of  claim 18 , wherein the counter is further configured for:
 counting a second fail bit count of the fourth failure memory cells verified as the reset failure after the fourth reset operation, and 
 the controller is further configured for:
 comparing the second fail bit count with a maximum correcting count of an error correcting operation to generate a comparison result, and performing an error bit correcting operation or ending a reset operation according to the comparison result.