Inventor
OFFEN ZEEV
US27 patents
⚠️ This page may combine multiple inventors who share the name “OFFEN ZEEV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
17 patentsUS10394300B2Aug 27, 2019
Controlling operating voltage of a processor
INTEL CORP10 citations92
US9996135B2Jun 12, 2018
Controlling operating voltage of a processor
INTEL CORP12 citations92
US9367114B2Jun 14, 2016
Controlling operating voltage of a processor
INTEL CORP19 citations92
US11175712B2Nov 16, 2021
Controlling operating voltage of a processor
INTEL CORP3 citations84
US6570573B1May 27, 2003
Method and apparatus for pre-fetching vertex buffers in a computer system
INTEL CORP17 citations81
US9395784B2Jul 19, 2016
Independently controlling frequency of plurality of power domains in a processor system
INTEL CORP3 citations73
US7290179B2Oct 30, 2007
System and method for soft error handling
INTEL CORP3 citations62
US8347035B2Jan 1, 2013
Posting weakly ordered transactions
INTEL CORP4 citations60
US10204051B2Feb 12, 2019
Technique to share information among different cache coherency domains
INTEL CORP0 citations52
US10078590B2Sep 18, 2018
Technique to share information among different cache coherency domains
INTEL CORP0 citations52
US9946650B2Apr 17, 2018
Technique to share information among different cache coherency domains
INTEL CORP0 citations52
US9898298B2Feb 20, 2018
Context save and restore
INTEL CORP1 citations52
US9035962B2May 19, 2015
Technique to share information among different cache coherency domains
INTEL CORP0 citations52
US9665488B2May 30, 2017
Technique to share information among different cache coherency domains
INTEL CORP0 citations51
US9239789B2Jan 19, 2016
Method and apparatus for monitor and MWAIT in a distributed cache architecture
INTEL CORP1 citations51
US10401928B2Sep 3, 2019
Interface for communication between circuit blocks of an integrated circuit, and associated apparatuses, systems, and methods
INTEL CORP0 citations49
US9594413B2Mar 14, 2017
Interface for communication between circuit blocks of an integrated circuit, and associated apparatuses, systems, and methods
INTEL CORP0 citations49
OFFEN ZEEV
4 patentsUS9081687B2Jul 14, 2015
Method and apparatus for MONITOR and MWAIT in a distributed cache architecture
OFFEN ZEEV8 citations81
US8643660B2Feb 4, 2014
Technique to share information among different cache coherency domains
OFFEN ZEEV2 citations61
US9035959B2May 19, 2015
Technique to share information among different cache coherency domains
OFFEN ZEEV0 citations51
US9035960B2May 19, 2015
Technique to share information among different cache coherency domains
OFFEN ZEEV0 citations51