Controlling operating voltage of a processor

Abstract

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

What is claimed is: 
     
       1. A multicore processor comprising:
 a first unit including a first plurality of cores and at least one cache memory; 
 a second unit including a second plurality of cores and at least one other cache memory; 
 a fabric to couple the first unit and the second unit; 
 one or more graphics processing units; and 
 a power control unit (PCU) to control an operating voltage from a voltage regulator to be provided to at least one of the first and second units, the PCU to cause the operating voltage to be updated according to a multi-level operating voltage ramp profile to a second level sufficient to support at least one core at a turbo mode frequency; 
 wherein the PCU is to send a plurality of requests to the voltage regulator to cause the voltage regulator to update the operating voltage to the second level according to the multi-level operating voltage ramp profile. 
 
     
     
       2. The multicore processor of  claim 1 , further comprising an image signal processor. 
     
     
       3. The multicore processor of  claim 1 , further comprising an integrated memory controller. 
     
     
       4. The multicore processor of  claim 1 , further comprising a Peripheral Component Interconnect Express (PCIe) interface. 
     
     
       5. The multicore processor of  claim 1 , wherein the at least one cache memory comprises a shared cache memory. 
     
     
       6. The multicore processor of  claim 1 , wherein the multicore processor comprises a system on chip. 
     
     
       7. The multicore processor of  claim 1 , wherein the multicore processor is to receive the operating voltage from an external voltage regulator. 
     
     
       8. The multicore processor of  claim 1 , wherein the first plurality of cores includes at least one second cache memory. 
     
     
       9. The multicore processor of  claim 1 , wherein the multi-level operating voltage ramp profile includes an interim voltage. 
     
     
       10. The multicore processor of  claim 9 , wherein the interim voltage is less than the second level. 
     
     
       11. A processor comprising:
 a plurality of cores and at least one cache memory; 
 at least one graphics processing unit; 
 a fabric to couple at least some of the plurality of cores and the at least one graphics processing unit; and 
 a power control unit (PCU) to control an operating voltage from a voltage regulator to be provided to at least some of the plurality of cores, wherein the PCU is to cause the operating voltage to be updated according to a multi-level operating voltage ramp profile to a second level sufficient to support at least one core at a turbo mode frequency; 
 wherein the PCU is to send a plurality of requests to the voltage regulator to cause the voltage regulator to update the operating voltage to the second level according to the multi-level operating voltage ramp profile, and to cause the at least one core to operate at the turbo mode frequency after the operating voltage has been updated to the second level. 
 
     
     
       12. The processor of  claim 11 , further comprising an image signal processor. 
     
     
       13. The processor of  claim 11 , further comprising an integrated memory controller. 
     
     
       14. The processor of  claim 11 , wherein the processor is to receive the operating voltage from an external voltage regulator. 
     
     
       15. A system comprising:
 a system on chip (SoC) comprising:
 a first unit including a first plurality of cores and at least one cache memory; 
 a second unit including a second plurality of cores and at least one other cache memory; 
 a fabric to couple the first unit and the second unit; 
 one or more graphics processing units; and 
 an integrated memory controller; 
 
 a power controller to control an operating voltage from a voltage regulator to be provided to at least one of the first and second units, the power controller to cause the operating voltage to be updated according to a multi-level operating voltage ramp profile to a second level sufficient to support at least one core at a turbo mode frequency; 
 wherein the power controller is to send a plurality of requests to the voltage regulator to cause the voltage regulator to update the operating voltage to the second level according to the multi-level operating voltage ramp profile; and 
 the voltage regulator coupled to the power controller. 
 
     
     
       16. The system of  claim 15 , wherein the SoC further comprises the power controller. 
     
     
       17. The system of  claim 15 , further comprising a display coupled to the SoC. 
     
     
       18. The system of  claim 16 , further comprising a system memory coupled to the SoC. 
     
     
       19. The system of  claim 15 , wherein the SoC further comprises an image signal processor. 
     
     
       20. The system of  claim 15 , wherein the multi-level operating voltage ramp profile includes an interim voltage, the interim voltage less than the second level.