Inventor

CHUA LINDA PEI EE

SG127 patents

⚠️ This page may combine multiple inventors who share the name “CHUA LINDA PEI EE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHUA LINDA PEI EE

STATS CHIPPAC LTD

Semiconductor device and method of forming through vias with reflowed conductive material

Method of making a wafer level integration package

Semiconductor package having through-hole via on saw streets formed with partial saw

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

Integrated circuit packaging system with film encapsulation and method of manufacture thereof

Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof

Integrated circuit packaging system with stacked die and method of manufacture thereof

Integrated circuit package-in-package system with wire-in-film encapsulant

Semiconductor die with through-hole via on saw streets and through-hole via in active area of die

Wafer level integration package

Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer

Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices

Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device

Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits

Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material

Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation

Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure

Semiconductor device and method of forming through vias with reflowed conductive material

Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation

Leadless package system having external contacts

Integrated circuit package system with conformal shielding and method of manufacture thereof

Integrated circuit packaging system and method of manufacture thereof

Integrated circuit package system with lead locking structure

Integrated circuit package system with rigid locking lead

Integrated circuit package system with package integration

Integrated circuit package-on-package system with anti-mold flash feature

Semiconductor device and method of using substrate with conductive posts and protective layers to form embedded sensor die package

Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die

PAGAILA REZA A

Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die

Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die

Semiconductor device and method of forming through vias with reflowed conductive material

Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation

Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars

Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars

Semiconductor device and method of forming through vias with reflowed conductive material

Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation

Semiconductor device and method of forming Fo-WLCSP with recessed interconnect area in peripheral region of semiconductor die

DO BYUNG TAI

Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer

Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices

Integrated circuit packaging system with lead encapsulation and method of manufacture thereof

Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor

Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device

Integrated circuit packaging system with trenched leadframe and method of manufacture thereof

Integrated circuit packaging system with trace protection layer and method of manufacture thereof

JCET SEMICONDUCTOR SHAOXING CO LTD

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

CHOW SENG GUAN

Integrated circuit package system with penetrable film adhesive

CHUA LINDA PEI EE

Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant

PAGAILA REZA ARGENTY

Exposed interconnect for a package on package system

STATS CHIPPAC PTE LTD

Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits