Inventor

GHODSI RAMIN

US76 patents

⚠️ This page may combine multiple inventors who share the name “GHODSI RAMIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GHODSI RAMIN

MICRON TECHNOLOGY INC

Pitch doubled circuit layout

Determining data states of memory cells

Data path with clock-data tracking

Apparatuses and methods for segmented SGS lines

Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells

Use of emerging non-volatile memory elements with flash memory

Trench memory structures and operation

Multi-cell resistive memory array architecture with select transistor

One-sided floating-gate memory cell

Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods

Determining data states of memory cells

I/O buffer offset mitigation

Programming memories with stepped programming pulses

Threshold voltage distribution determination

Memory timing self-calibration

Multi-element resistive memory

Power on reset circuitry in electronic systems

Apparatuses and methods for segmented SGS lines

Startup circuit and method

Startup circuit and method

Use of emerging non-volatile memory elements with flash memory

Controlling a memory device responsive to degradation

NAND flash memory programming

One-sided floating-gate memory cell

Apparatus for determining data states of memory cells

I/O buffer offset mitigation while applying a same voltage level to two inputs of an input buffer

I/O buffer offset mitigation

Determining data states of memory cells

Programming memories with stepped programming pulses

Apparatuses and methods for reducing read disturb

Programming memories with stepped programming pulses including inhibiting a memory cell for a portion of a programming pulse and enabling that memory cell for another portion of that programming pulse

Erasable block segmentation for memory

Applying substantially the same voltage differences across memory cells at different locations along an access line while programming

Apparatuses and methods for segmented SGS lines

I/O buffer offset mitigation

Memories for determining data states of memory cells

Memory system data management

Apparatus for determining data states of memory cells

Apparatus for determining data states of memory cells

Functional data programming in a non-volatile memory

Ladder-based high speed switch regulator

Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods

Apparatuses and methods and for providing power responsive to a power loss

INTEL CORP

Methods and apparatus to read memory cells based on clock pulse counts

Methods and apparatus to read memory cells based on clock pulse counts

Methods and apparatus to read memory cells based on clock pulse counts

GHODSI RAMIN

Erasable block segmentation for memory

Trench memory structure operation

HA CHANG WAN

Controlling a memory device responsive to degradation

ROUND ROCK RES LLC

Layout for high density conductive interconnects