Multi-element resistive memory

Abstract

A memory device, and methods relating thereto, having memory cells in which a single an access transistor controls the grounding of at least two storage resistive memory elements, such as resistive storage elements, for purposes of reading the respective logical states of the storage elements. The logical states of the storage elements are decoupled from one another and are read independently. The storage elements are disposed in respective layers. Each storage element is coupled to first and second conductors having for reading the memory that have respective, parallel, longitudinal axes. The longitudinal axes are oriented substantially parallel to one another, at least in proximity to a particular storage element.

1. A magnetic random access memory cell comprising:
 a first magnetic storage element having a first sense layer and a first pinned layer;  
 a second magnetic storage element having a second sense layer and a second pinned layer, said first and second sense layers being mutually electrically coupled through first and second read conductors, said first and second read conductors having respective longitudinal axes, said first and second pinned layers being electrically coupled to respective first and second read/write conductors, said first and second read/write conductors having at least localized longitudinal axes in respective vicinities of said first and second magnetic storage elements, said at least localized longitudinal axes of said first read/write conductor being oriented substantially parallel to said longitudinal axis of said first read conductor;  
 a switching device coupled to said mutually coupled pinned layers through said first and second read conductors and configured to couple said mutually coupled pinned layers to a conductor for receiving a substantially constant potential.  
 
     
     
       2. A magnetic random access memory cell as defined in  claim 1  wherein said substantially constant potential comprises a ground potential. 
     
     
       3. A magnetic random access memory cell as defined in  claim 1  wherein said first magnetic storage element and said second magnetic storage element are disposed above said switching device in a first direction, and wherein said switching device is disposed adjacent to a second switching device of a second magnetic random access memory cell. 
     
     
       4. A memory device comprising:
 a plurality of read/write conductors respectively paired with a plurality of read conductors, said respectively paired read/write and read conductors having substantially parallel longitudinal axes; and  
 at least one memory cell electrically coupled to each said respectively paired read/write conductor and read conductor, said at least one memory cell including a transistor and two resistive memory elements, said two resistive memory elements being electrically connected in series by respective said read conductors, said two resistive memory elements being mutually coupled to said transistor at a common node.  
 
     
     
       5. A memory device as defined in  claim 4  wherein:
 said two resistive memory elements each include a pinned layer and a sense layer; and  
 wherein said sense layer of each said resistive memory element is electrically coupled through said transistor to a conductor for receiving a substantially constant electrical potential.  
 
     
     
       6. A memory device as in  claim 5  wherein said substantially constant electrical potential is a ground potential. 
     
     
       7. A memory device as defined in  claim 4  wherein said transistor comprises:
 two transistors having a common drain connection and respective gate terminals, said gate terminals mutually coupled to one another.  
 
     
     
       8. A memory device as defined in  claim 4  wherein:
 said first and second resistive memory elements are disposed in layered spaced relation to one another above said transistor.  
 
     
     
       9. A memory device as defined in  claim 4  further comprising:
 a word line conductor electrically coupled to a gate of said transistor.  
 
     
     
       10. A memory integrated circuit comprising:
 a first two-dimensional array of resistive memory elements disposed in substantially parallel spaced relation between a second two-dimensional array of resistive memory elements and a third two-dimensional array of isolation devices, each isolation device of said third two-dimensional array being coupled to at least one resistive memory element of said first two-dimensional array and at least another resistive memory element of said second two-dimensional array;  
 a first plurality of read/write conductors having respective longitudinal axes oriented in a first direction and coupled to said first two-dimensional array of resistive memory elements; and  
 a second plurality of read conductors having respective longitudinal axes also oriented in said first direction and also coupled to said first two-dimensional array of resistive memory elements.  
 
     
     
       11. A memory integrated circuit as defined in  claim 10  wherein said first array of resistive memory elements comprises an array of MRAM memory elements. 
     
     
       12. A memory integrated circuit as defined in  claim 10  wherein said first array of resistive memory elements comprises an array of progrmamable conductive memory elements. 
     
     
       13. A memory integrated circuit as defined in  claim 10  further comprising:
 a sensing circuit, said sensing circuit adapted to sense a state of said resistive memory elements during a time interval when a respective isolation device is activated.  
 
     
     
       14. A memory integrated circuit comprising:
 a plurality of memory cells, each cell including:  
 first and second resistive memory storage elements, said first and second resistive memory storage elements being electrically coupled to respective first and second memory sensing circuits, said first and second resistive memory storage elements being mutually coupled to a reference potential through a common dual transistor.  
 
     
     
       15. A memory integrated circuit as defined in  claim 14  wherein said first and second resistive memory storage elements are disposed in spaced relation above said common dual transistor. 
     
     
       16. A memory integrated circuit as defined in  claim 14  further comprising an address decoder electrically coupled to first and second gates of said dual transistor and adapted to activate said dual transistor in response to an address signal received at an address input of said address decoder. 
     
     
       17. A magnetic random access memory device comprising:
 a semiconductor substrate having an upper surface;  
 a transistor having a drain region supported by said semiconductor substrate;  
 a first magnetic random access memory storage element over said upper surface and above said drain region and electrically coupled to said drain region through a first read conductor, said first read conductor having a first longitudinal axis;  
 a second magnetic random access memory storage element over said upper surface and above said first magnetic random access memory storage element and electrically coupled to said first magnetic random access memory storage element and said drain region through a second read conductor, said second read conductor having a second longitudinal axis; and  
 first and second read/write conductors having respective third and fourth longitudinal axes, said first longitudinal axis being disposed substantially parallel to said third longitudinal axis, said second longitudinal axis being disposed substantially parallel to said fourth longitudinal axis.  
 
     
     
       18. A programmable conductive memory device comprising:
 a semiconductor substrate having an upper surface;  
 a transistor having a drain region supported by said semiconductor substrate;  
 a first programmable conductive memory storage element disposed above said upper surface and electrically coupled to said drain region by a first read conductor, said first read conductor having a first longitudinal axis;  
 a second programmable conductive memory storage element disposed above said first programmable conductive memory storage element and electrically coupled to said first programmable conductive memory storage element and said drain region through a second read conductor, said second read conductor having a second longitudinal axis; and  
 first and second read/write conductors having respective third and fourth longitudinal axes, said first longitudinal axis being disposed substantially parallel to said third longitudinal axis, said second longitudinal axis being disposed substantially parallel to said fourth longitudinal axis.  
 
     
     
       19. A method of manufacturing  forming a digital data storage  memory device, comprising:
 forming a transistor layer, including a plurality of transistors,  over a semiconductor substrate, said transistor layer comprising an array of transistors;  
 forming a first resistive  memory storage  layer over said transistor layer, said first resistive  memory storage  layer comprising a plurality of first resistive memory storage structures  elements, each of said plurality of first resistive memory storage structures including respectively paired  and a plurality of first read conductors and first read/write conductors, said first read conductors and said first read/write conductors being respectively coupled with said plurality of first resistive memory elements, wherein said first read conductors and said first read/write conductors each have a  respective first longitudinal axis and said longitudinal axes of said respectively paired read conductors and read/write conductors  axes, which are disposed in a  substantially parallel relationship ;  
 forming a second magnetic  memory storage  layer over said first magnetic  memory storage  layer, said second magnetic  memory storage  layer comprising a plurality of second magnetic  resistive memory storage structures  elements, and a plurality of second read conductors and second read/write conductors, said second read conductors and said second read/write conductors being respectively coupled with said plurality of first resistive memory elements, wherein said second read conductors and said second read/write conductors each have respective second longitudinal axes, which are substantially parallel to said first longitudinal axes; and  
 electrically coupling respective ones of said plurality of  said transistors, said plurality of  first magnetic memory storage structures  read conductors, and said plurality of  second magnetic memory storage structures  read conductors.  
 
     
     
       20. A  The method of manufacturing a digital data storage device as defined in   claim 19 , further comprising forming a control circuit over said semiconductor substrate, said control circuit being configured for activating  said plurality of transistors, said plurality of first resistive memory elements, and said plurality of second resistive memory elements in a three- dimensional memory array comprising said transistor layer, said first memory layer and said second memory layer.    
     
     
       21. A processing system comprising:
 a plurality of memory cells, each cell including:  
 first and second resistive memory storage elements, said first and second resistive memory storage elements being electrically coupled to respective first and second memory sensing circuits, said first and second resistive memory storage elements being mutually coupled to a reference potential through a wired-NOR FLASH memory transistor.  
 
     
     
       22. A method of forming a memory device comprising:
 forming a plurality of NOR FLASH-memory transistors disposed in an array over a semiconductor substrate;  
 forming an array of first resistive memory elements over said transistors;  
 forming an array of second resistive memory elements over said first resistive memory elements; and  
 electrically coupling at least one second resistive memory element to a respective first resistive memory element and to a respective transistor.  
 
     
     
       23. A memory device comprising:
   a first magnetic storage element and a second magnetic storage element, wherein said first and second magnetic storage elements are electrically coupled through associated respective first and second read conductors and said first and second read conductors have substantially parallel respective first longitudinal axes;        respective first and second read/write conductors electrically coupled to said first and second magnetic storage elements, said first and second read/write conductors having substantially parallel respective second longitudinal axes, said first longitudinal axes are substantially parallel to said second longitudinal axes;        respective first and second write conductors associated with said first and second magnetic storage elements, wherein said first and second write conductors have substantially parallel third longitudinal axes which are non - parallel relative to said first and second longitudinal axes; and        a switching device coupled to said first and second read conductors.      
     
     
       24. The memory device of  claim 23 , wherein said switching device is configured to couple said first and second read conductors to a constant potential conductor.  
     
     
       25. The memory device of  claim 24 , wherein said constant potential conductor is a ground potential conductor.  
     
     
       26. The memory device of  claim 23 , wherein said switching device comprises an access transistor.  
     
     
       27. The memory device of  claim 23 , wherein said first read/write conductor is over said first magnetic storage element, wherein said first magnetic storage element is over said first write conductor, and wherein said first write conductor is over said first write conductor.  
     
     
       28. The memory device of  claim 23 , wherein said first write conductor is over said second read/write conductor, wherein said second read/write conductor is over said second magnetic storage element, wherein said second magnetic storage element is over said second read conductor, wherein said second read conductor is over said second write conductor, wherein said second write conductor is over said switching device, and wherein said switching device is over a substrate.  
     
     
       29. The memory device of  claim 23 , wherein said third longitudinal axes are at an oblique angle relative to said first and second longitudinal axes.  
     
     
       30. The memory device of  claim 23 , wherein said third longitudinal axes are substantially orthogonal to said first and second longitudinal axes.  
     
     
       31. A memory device, comprising:
   an array of memory cells, each said memory cell comprising at least two memory elements electrically coupled to a common read circuit and therethrough to an access transistor, said access transistor being connected to one of a plurality of wordlines, wherein each of said two memory elements is also electrically coupled to a respective read/write line; and        wherein a sneak path resistance for reading one of said memory cells is determined by the formula  (( n+ 1   )/( n− 1   ))· R/M, where R is the resistance value for one of said memory elements, n is the number of wordlines of said array and M is the number of memory elements in each of said memory cells.      
     
     
       32. The memory device of  claim 31 , wherein said access transistor is paired with a second access transistor in a NOR architecture.  
     
     
       33. The memory device of  claim 31 , wherein each of said memory cells has exactly two memory elements.  
     
     
       34. The memory device of  claim 31 , wherein said memory elements are MRAM memory elements.  
     
     
       35. A method of reading a memory device comprising a memory cell comprising at least two memory elements electrically coupled to one another by respective read lines and each said memory element being connected to a respective read/write line, wherein said read lines of said memory cells are electrically coupled to a respective access transistor and a wordline respectively coupled to a gate of said access transistor, said method comprising:
   electrically connecting said at least two memory elements to ground by activating said wordline;        selecting a read/write line associated with one of said at least two memory elements; and        sensing the resistivity state of the memory element associated with the selected read/write line as a logic state while allowing the other of said at least two memory elements to float.      
     
     
       36. The method of  claim 35 , wherein said sensing the resistivity detects a voltage of the read/write line.  
     
     
       37. The method of  claim 35 , wherein said sensing the resistivity detects a current into the read/write line.  
     
     
       38. A method of writing a memory device comprising a plurality of memory cells, each comprising at least first and second memory elements electrically coupled to one another by respective read lines and each said memory element being connected to a respective read/write line and associated with a respective write line, wherein respective said read lines of each said memory cell are electrically coupled to a respective access transistor, said method comprising:
   addressing said first memory element by selecting a respective read/write line and write line;        supplying a first write current to the respective read/write line; and        supplying a second write current to the respective write line.      
     
     
       39. The method of  claim 38 , wherein said addressing a memory element comprises activating a read/write line write address decoder and a write line write address decoder.  
     
     
       40. The method of  claim 38 , wherein said supplying of first and second write currents forms a localized magnetic field at said first memory element.  
     
     
       41. The method of  claim 38 , further comprising restoring said first memory element to a read mode.