Inventor
KOUNAVIS MICHAEL E
US83 patents
⚠️ This page may combine multiple inventors who share the name “KOUNAVIS MICHAEL E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
45 patentsUS7408932B2Aug 5, 2008
Method and apparatus for two-stage packet classification using most specific filter matching and transport level sharing
INTEL CORP106 citations97
US10585809B2Mar 10, 2020
Convolutional memory integrity
INTEL CORP28 citations94
US10860709B2Dec 8, 2020
Encoded inline capabilities
INTEL CORP25 citations93
US7958436B2Jun 7, 2011
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP13 citations92
US7525958B2Apr 28, 2009
Apparatus and method for two-stage packet classification using most specific filter matching and transport level sharing
INTEL CORP31 citations92
US12050701B2Jul 30, 2024
Cryptographic isolation of memory compartments in a computing environment
INTEL CORP3 citations86
US11580234B2Feb 14, 2023
Implicit integrity for cryptographic computing
INTEL CORP6 citations86
US11354423B2Jun 7, 2022
Cryptographic isolation of memory compartments in a computing environment
INTEL CORP5 citations84
US11321469B2May 3, 2022
Microprocessor pipeline circuitry to support cryptographic computing
INTEL CORP5 citations84
US11308225B2Apr 19, 2022
Management of keys for use in cryptographic computing
INTEL CORP5 citations84
US11048579B2Jun 29, 2021
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP3 citations84
US11010310B2May 18, 2021
Convolutional memory integrity
INTEL CORP7 citations84
US10379938B2Aug 13, 2019
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP4 citations84
US10256971B2Apr 9, 2019
Flexible architecture and instruction for advanced encryption standard (AES)
INTEL CORP2 citations84
US9645884B2May 9, 2017
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP5 citations84
US9116684B2Aug 25, 2015
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP4 citations84
US8861847B2Oct 14, 2014
System and method for adaptive skin tone detection
INTEL CORP13 citations84
US8769385B2Jul 1, 2014
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP4 citations84
US7991152B2Aug 2, 2011
Speeding up Galois Counter Mode (GCM) computations
INTEL CORP7 citations84
US11784786B2Oct 10, 2023
Mitigating security vulnerabilities with memory allocation markers in cryptographic computing systems
INTEL CORP4 citations74
US11575504B2Feb 7, 2023
Cryptographic computing engine for memory load and store units of a microarchitecture pipeline
INTEL CORP5 citations74
US8856627B2Oct 7, 2014
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP3 citations74
US8793559B2Jul 29, 2014
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP3 citations74
US8775912B2Jul 8, 2014
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP3 citations74
US8775911B2Jul 8, 2014
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP3 citations74
US8775910B2Jul 8, 2014
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP3 citations74
US8769386B2Jul 1, 2014
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP3 citations74
US11899530B2Feb 13, 2024
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
INTEL CORP0 citations73
US11693754B2Jul 4, 2023
Aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates
INTEL CORP2 citations73
US11301344B2Apr 12, 2022
Aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates
INTEL CORP3 citations73
US10540198B2Jan 21, 2020
Technologies for memory replay prevention using compressive encryption
INTEL CORP3 citations73
US10223528B2Mar 5, 2019
Technologies for deterministic code flow integrity protection
INTEL CORP2 citations73
US9575566B2Feb 21, 2017
Technologies for robust two-dimensional gesture recognition
INTEL CORP3 citations71
US12386651B2Aug 12, 2025
Technologies for memory replay prevention using compressive encryption
INTEL CORP0 citations63
US11775332B2Oct 3, 2023
Technologies for memory replay prevention using compressive encryption
INTEL CORP0 citations63
US11704297B2Jul 18, 2023
Collision-free hashing for accessing cryptographic computing metadata and for cache expansion
INTEL CORP0 citations63
US11429580B2Aug 30, 2022
Collision-free hashing for accessing cryptographic computing metadata and for cache expansion
INTEL CORP0 citations63
US11275603B2Mar 15, 2022
Technologies for memory replay prevention using compressive encryption
INTEL CORP0 citations63
US10581590B2Mar 3, 2020
Flexible architecture and instruction for advanced encryption standard (AES)
INTEL CORP0 citations63
US10554386B2Feb 4, 2020
Flexible architecture and instruction for advanced encryption standard (AES)
INTEL CORP0 citations63
US10331944B2Jun 25, 2019
Technologies for dynamic performance of image analysis
INTEL CORP1 citations63
US10313107B2Jun 4, 2019
Flexible architecture and instruction for advanced encryption standard (AES)
INTEL CORP0 citations63
US10270589B2Apr 23, 2019
Flexible architecture and instruction for advanced encryption standard (AES)
INTEL CORP0 citations63
US10263769B2Apr 16, 2019
Flexible architecture and instruction for advanced encryption standard (AES)
INTEL CORP0 citations63
US10262397B2Apr 16, 2019
Image de-noising using an equalized gradient space
INTEL CORP1 citations63
KING STEVEN R
3 patentsUS8713416B2Apr 29, 2014
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
KING STEVEN R3 citations73
US8413024B2Apr 2, 2013
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
KING STEVEN R4 citations73
US8225184B2Jul 17, 2012
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
KING STEVEN R3 citations73
GUERON SHAY
1 patentMATHEW SANU K
1 patentShowing the top 50 of 83 patents by PatentIndex Score.