Inventor

LANGHAMMER MARTIN

GB266 patents

⚠️ This page may combine multiple inventors who share the name “LANGHAMMER MARTIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LANGHAMMER MARTIN

ALTERA CORP

Programmable logic devices with function-specific blocks

Programmable logic device including multipliers and configurations thereof to reduce resource utilization

Devices and methods with programmable logic and digital signal processing regions

Configuring floating point operations in a programmable logic device

FPGA configuration bitstream protection using multiple keys

Programmable logic device with specialized multiplier blocks

Devices and methods with programmable logic and digital signal processing regions

Programmable logic device with routing channels

Large multiplier for programmable logic device

FPGA configuration bitstream encryption using modified key

DSP processor architecture with write datapath word conditioning and analysis

Devices and methods with programmable logic and digital signal processing regions

Programmable device using fixed and configurable logic to implement recursive trees

Flexible high speed forward error correction (FEC) physical medium attachment (PMA) and physical coding sublayer (PCS) connection system

Digital signal processing blocks with embedded arithmetic circuits

Multiple-precision processing block in a programmable integrated circuit device

Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry

Embedded floating-point operator circuitry

Fused floating point datapath with correct rounding

Parallel finite field vector operators

Adder-rounder circuitry for specialized processing block in programmable logic device

Multi-functional digital signal processing circuitry

Programmable logic device with routing channels

Normalization implementation for a logmap decoder

Programmable device implementing fixed and floating point functionality in a mixed architecture

One-time programmable memories for key storage

Encryption key obfuscation and storage

Programmable logic device with specialized functional block

Logic cell supporting addition of three binary words

Programmable logic device including multipliers and configurations thereof to reduce resource utilization

Programmable logic device including multipliers and configurations thereof to reduce resource utilization

Devices and methods with programmable logic and digital signal processing regions

Circuitry for arithmetically accumulating a succession of arithmetic values

Specialized processing block for programmable logic device

Specialized processing block for programmable logic device

Security RAM block

Method and apparatus for protecting designs in SRAM-based programmable logic devices

Variable precision floating-point multiplier

Circuitry and methods for continuous parallel decoder operation

LANGHAMMER MARTIN

Specialized processing block with fixed- and floating-point structures

Implementing mixed-precision floating-point operations in a programmable integrated circuit device

Configuring a programmable integrated circuit device to perform matrix multiplication

Combined floating point adder and subtractor

AES core with independent inputs and outputs

Large multiplier for programmable logic device

Specialized processing block for programmable logic device

INTEL CORP

High performance regularized network-on-chip architecture

ALTERA CORPORATIONS

Programmable logic device including multipliers and configurations thereof to reduce resource utilization

LEE KWAN YEE MARTIN

Specialized processing block for programmable logic device

ALTER CORP

Integrated circuits with reduced interconnect overhead