P

Inventor

XANTHOPOULOS THUCYDIDES

US13 patents
⚠️ This page may combine multiple inventors who share the name “XANTHOPOULOS THUCYDIDES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MARVELL ASIA PTE LTD

6 patents
US11545981B1Jan 3, 2023

DLL-based clocking architecture with programmable delay at phase detector inputs

MARVELL ASIA PTE LTD12 citations84
US11402413B1Aug 2, 2022

Droop detection and mitigation

MARVELL ASIA PTE LTD9 citations84
US10784871B1Sep 22, 2020

Clocking architecture for DVFS with low-frequency DLL locking

MARVELL ASIA PTE LTD14 citations84
US12519476B1Jan 6, 2026

DLL-based clocking architecture with programmable delay at phase detector inputs

MARVELL ASIA PTE LTD0 citations61
US11669419B1Jun 6, 2023

System and method for performing a failure assessment of an integrated circuit

MARVELL ASIA PTE LTD2 citations60
US11545987B1Jan 3, 2023

Traversing a variable delay line in a deterministic number of clock cycles

MARVELL ASIA PTE LTD1 citations59

CAVIUM INC

3 patents
US9570128B2Feb 14, 2017

Managing skew in data signals

CAVIUM INC2 citations71
US9483100B2Nov 1, 2016

Method and apparatus for power gating hardware components in a chip device

CAVIUM INC0 citations51
US9721627B2Aug 1, 2017

Method and apparatus for aligning signals

CAVIUM INC0 citations48

CAVIUM NETWORKS INC

1 patent
US7209531B1Apr 24, 2007

Apparatus and method for data deskew

CAVIUM NETWORKS INC52 citations95

MARVELL INT LTD

1 patent
US10530370B1Jan 7, 2020

Glitch-free PLL Multiplexer

MARVELL INT LTD16 citations83

CRAIN ETHAN

1 patent
US8634509B2Jan 21, 2014

Synchronized clock phase interpolator

CRAIN ETHAN7 citations76

XANTHOPOULOS THUCYDIDES

1 patent
US9263151B2Feb 16, 2016

Memory interface with selectable evaluation modes

XANTHOPOULOS THUCYDIDES1 citations45