Traversing a variable delay line in a deterministic number of clock cycles

Abstract

In an embodiment, a method includes initializing an input clock rotating register by sending a reset signal synchronized to an input clock signal and initializing an output clock rotating register by sending the reset signal synchronized to an output clock signal. The method further providing a data input synchronized to the output clock to a plurality of mux-flops. The output clock rotating register activates one of the plurality of mux-flops to receive the data input. The method further includes forwarding the data input via the one of the plurality of mux-flops to a multiplexer. The multiplexer has a selection input of the input clock rotating register. The method further includes selecting the data input as the output of the multiplexer to be a data output signal, such that the data output is synchronized with the input clock.

What is claimed is: 
     
       1. A method comprising:
 initializing an input clock rotating register by sending a reset signal, wherein the reset signal received by the input clock rotating register is synchronized to an input clock signal; 
 initializing an output clock signal via a variable delay line, the variable delay line configured to delay the input clock signal based on a number of offset cycles provided to the variable delay line; 
 initializing an output clock rotating register by sending the reset signal, wherein the reset signal received by the output clock rotating register is synchronized to the output clock signal; 
 providing a data input synchronized to the output clock signal to a plurality of mux-flops, wherein the output clock rotating register activates one of the plurality of mux-flops to receive the data input; 
 forwarding the data input via the one of the plurality of mux-flops to a multiplexer, wherein the multiplexer is coupled to receive the outputs of the plurality of mux-flops as data inputs and wherein the input clock rotating register controls the data input selected by the multiplexer as its output; and 
 selecting the data input as the output of the multiplexer to be a data output signal, such that the data output is synchronized with the input clock. 
 
     
     
       2. The method of  claim 1 , further comprising:
 synchronizing the reset signal to the input clock signal by routing the reset signal through a first flop that uses the input clock signal; and 
 synchronizing the reset signal to the output clock signal by routing the reset signal through a second flop that uses the output clock signal. 
 
     
     
       3. The method of  claim 1 , wherein:
 a number of flops in the input clock rotating register and a number of flops in the output clock rotating register are equal, 
 each mux-flop is coupled to be activated to receive the data input by a particular flop of the input clock rotating register, and each mux-flop is coupled to output to a particular input of the multiplexer. 
 
     
     
       4. The method of  claim 1 , wherein upon sending the reset signal, the input clock signal and output clock signal have a period longer than that of the reset signal, and further comprising:
 after sending the reset signal, increasing the frequency of the input clock signal and the output clock signal. 
 
     
     
       5. The method of  claim 1 , wherein initializing the input clock rotating register and initializing the output clock rotating register further includes:
 setting values of the output clock rotating register such that, in a given clock cycle, one mux-flop of the plurality of mux-flops receives the data input signal; 
 setting values of the input clock rotating register such that, in a given clock cycle, the multiplexer outputs a value stored by a mux-flop loaded according to the number of offset cycles. 
 
     
     
       6. The method of  claim 5 , wherein the offset is equal to one fewer than a number of the plurality of mux-flops. 
     
     
       7. The method of  claim 1 , wherein the data output signal is provided through a Joint Test Action Group (JTAG) interface. 
     
     
       8. A system comprising:
 an input clock rotating register configured to be initialized by a reset signal, wherein the reset signal received by the input clock rotating register is synchronized to an input clock signal; 
 an output clock rotating register configured to be initialized by the reset signal, wherein the reset signal received by the output clock rotating register is synchronized to an output clock signal, the output clock signal initialized via a variable delay line, the variable delay line configured to delay the input clock signal based on a number of offset cycles provided to the variable delay line; 
 a plurality of mux-flops configured to receive a data input synchronized to the output clock signal, wherein the output clock signal rotating register activates one of the plurality of mux-flops to receive the data input; and 
 a multiplexer configured to receive the data input, via the plurality of mux-flops, the multiplexer receiving a selection input of the input clock rotating register, wherein the multiplexer selects the data input as the output of the multiplexer using the selection input to be a data output signal, such that the data output is synchronized with the input clock. 
 
     
     
       9. The system of  claim 8 , further comprising:
 a first flop configured to synchronize the reset signal to the input clock signal by receiving the reset signal as a data input and the input clock signal as a clock input; and 
 a second flop configured to synchronize the reset signal to the output clock signal by receiving the reset signal as a data input and the output clock signal as a clock input. 
 
     
     
       10. The system of  claim 8 , wherein:
 a number of flops in the input clock rotating register and a number of flops in the output clock rotating register are equal, 
 each mux-flop is coupled to be activated to receive the data input by a particular flop of the input clock rotating register, and each mux-flop is coupled to output to a particular input of the multiplexer. 
 
     
     
       11. The system of  claim 8 , wherein upon sending the reset signal, the input clock signal and output clock signal have a period longer than that of the reset signal, and after sending the reset signal, the frequency of the input clock signal and the output clock signal are increased. 
     
     
       12. The system of  claim 8 , wherein initializing the input clock rotating register and initializing the output clock rotating register further includes:
 setting values of the output clock rotating register such that, in a given clock cycle, one mux-flop of the plurality of mux-flops receives the data input signal; 
 setting values of the input clock rotating register such that, in a given clock cycle, the multiplexer outputs a value stored by a mux-flop loaded according to the number of offset cycles. 
 
     
     
       13. The system of  claim 12 , wherein the offset is equal to one fewer than a number of the plurality of mux-flops. 
     
     
       14. The system of  claim 12 , wherein the data output signal is provided through a Joint Test Action Group (JTAG) interface. 
     
     
       15. A non-transitory computer readable medium storing instructions thereon, the instructions, when executed by a processor, cause the processor to:
 initialize an input clock rotating register by sending a reset signal, wherein the reset signal received by the input clock rotating register is synchronized to an input clock signal; 
 initialize an output clock signal via a variable delay line, the variable delay line configured to delay the input clock signal based on a number of offset cycles provided to the variable delay line; 
 initialize an output clock rotating register by sending the reset signal, wherein the reset signal received by the output clock rotating register is synchronized to an output clock signal; 
 provide a data input synchronized to the output clock signal to a plurality of mux-flops, wherein the output clock rotating register activates one of the plurality of mux-flops to receive the data input; 
 forward the data input via the one of the plurality of mux-flops to a multiplexer, wherein the multiplexer is coupled to receive the outputs of the plurality of mux-flops as data inputs and wherein the input clock rotating register controls the data input selected by the multiplexer as its output; and 
 select the data input as the output of the multiplexer to be a data output signal, such that the data output is synchronized with the input clock. 
 
     
     
       16. The non-transitory computer readable medium of  claim 15 , wherein the instructions further cause the processor to:
 synchronize the reset signal to the input clock signal by routing the reset signal through a first flop that uses the input clock signal; and 
 synchronizing the reset signal to the output clock signal by routing the reset signal through a second flop that uses the output clock signal. 
 
     
     
       17. The non-transitory computer readable medium of  claim 15 , wherein:
 a number of flops in the input clock rotating register and a number of flops in the output clock rotating register are equal, 
 each mux-flop is coupled to be activated to receive the data input by a particular flop of the input clock rotating register, and each mux-flop is coupled to output to a particular input of the multiplexer. 
 
     
     
       18. The non-transitory computer readable medium of  claim 15 , wherein upon sending the reset signal, the input clock signal and output clock signal have a period longer than that of the reset signal, and further comprising:
 after sending the reset signal, increasing the frequency of the input clock signal and the output clock signal. 
 
     
     
       19. The non-transitory computer readable medium of  claim 15 , wherein initializing the input clock rotating register and initializing the output clock rotating register further includes:
 setting values of the output clock rotating register such that, in a given clock cycle, one mux-flop of the plurality of mux-flops receives the data input signal; 
 setting values of the input clock rotating register such that, in a given clock cycle, the multiplexer outputs a value stored by a mux-flop loaded according to the number of offset cycles. 
 
     
     
       20. The non-transitory computer readable medium of  claim 19 , wherein the offset is equal to one fewer than a number of the plurality of mux-flops.