Inventor

IGNATOWSKI MICHAEL

US52 patents

⚠️ This page may combine multiple inventors who share the name “IGNATOWSKI MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IGNATOWSKI MICHAEL

ADVANCED MICRO DEVICES INC

Die-stacked memory device with reconfigurable logic

Die-stacked memory device with reconfigurable logic

Near-memory hardened compute blocks for configurable computing substrates

Nondeterministic memory access requests to non-volatile memory

Computation memory operations in a logic layer of a stacked memory

Latency-aware memory control

Flexible, scalable graph-processing accelerator

Device and method for accelerating matrix multiply operations

Data processing system with decoupled data operations

Memory page access detection

Tolerating memory stack failures in multi-stack systems

Method and apparatus of integrating memory stacks

Device and method for accelerating matrix multiply operations

Error detection and correction in memory modules using programmable ECC engines

Method for a reliability, availability, and serviceability-conscious huge page support

Method and apparatus of integrating memory stacks

Providing host-based error detection capabilities in a remote execution device

Method for a reliability, availability, and serviceability-conscious huge page support

Device and method for accelerating matrix multiply operations

Flexible, scalable graph-processing accelerator

Memory sprinting

Memory sprinting

Ferroelectric random-access memory with enhanced lifetime, density, and performance

Register, flop, and latch designs inlcuding ferroelectric and linear dielectrics

Memory object tagged memory monitoring method and system

Multi-protocol header generation system

Methods and systems for mitigating memory drift

Write endurance management techniques in the logic layer of a stacked memory

Device and method for accelerating matrix multiply operations as a sum of outer products

IBM

Integrated processing and L2 DRAM cache

Multi-port multiple-simultaneous-access DRAM chip

Multiple-core processor supporting multiple instruction set architectures

Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls

Method for dynamically managing power in microprocessor chips according to present processing demands

Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data

Method and system of an integrated simulation tool using business patterns and scripts

Apparatus and method for modeling queueing systems with highly variable traffic arrival rates

Method, system and article of manufacture for an analytic modeling technique for handling multiple objectives

Multiprocessor system with dynamic cache coherency regions

Apparatus for modeling queueing systems with highly variable traffic arrival rates

System and computer program product for dynamically managing power in microprocessor chips according to present processing demands

LOH GABRIEL H

Die-stacked memory device providing data translation

Stacked memory device with metadata management

Cache coherency using die-stacked memory device with logic die

BERNSTEIN KERRY

Semiconductor chip stacking for redundancy and yield improvement

Semiconductor chip stacking for redundancy and yield improvement

HSU LISA R

Quality of service support using stacked memory device with logic die

RYMARCZYK JAMES WALTER

Multiple-core processor supporting multiple instruction set architectures

DALY DAVID MICHAEL

Systems and methods for masking latency of memory reorganization work in a compressed memory system

MAYHEW DAVID

Method and apparatus for controlling state information retention in an apparatus