Inventor
RHODEHAMEL MICHAEL W
US26 patents
Patents
26 patentsUS5623628AApr 22, 1997
Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
INTEL CORP296 citations98
US5581782ADec 3, 1996
Computer system with distributed bus arbitration scheme for symmetric and priority agents
INTEL CORP117 citations98
USRE38388EJan 13, 2004
Method and apparatus for performing deferred transactions
INTEL CORP50 citations96
US5809524ASep 15, 1998
Method and apparatus for cache memory replacement line identification
INTEL CORP57 citations96
US5796977AAug 18, 1998
Highly pipelined bus architecture
INTEL CORP89 citations96
US5754833AMay 19, 1998
Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio
INTEL CORP77 citations96
US5715428AFeb 3, 1998
Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system
INTEL CORP82 citations96
US5682516AOct 28, 1997
Computer system that maintains system wide cache coherency during deferred communication transactions
INTEL CORP58 citations96
US5615343AMar 25, 1997
Method and apparatus for performing deferred transactions
INTEL CORP69 citations96
US5636374AJun 3, 1997
Method and apparatus for performing operations based upon the addresses of microinstructions
INTEL CORP68 citations94
US5832534ANov 3, 1998
Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
INTEL CORP43 citations93
US6061599AMay 9, 2000
Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair
INTEL CORP31 citations92
US5909699AJun 1, 1999
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
INTEL CORP19 citations92
US5845107ADec 1, 1998
Signaling protocol conversion between a processor and a high-performance system bus
INTEL CORP36 citations92
US5802132ASep 1, 1998
Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
INTEL CORP33 citations92
US5797026AAug 18, 1998
Method and apparatus for self-snooping a bus during a boundary transaction
INTEL CORP41 citations92
US5764934AJun 9, 1998
Processor subsystem for use with a universal computer architecture
INTEL CORP41 citations92
US5701503ADec 23, 1997
Method and apparatus for transferring information between a processor and a memory system
INTEL CORP27 citations92
US5572702ANov 5, 1996
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
INTEL CORP40 citations92
US5515516AMay 7, 1996
Initialization mechanism for symmetric arbitration agents
INTEL CORP22 citations92
US6055656AApr 25, 2000
Control register bus access through a standardized test access port
INTEL CORP27 citations89
US5784579AJul 21, 1998
Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth
INTEL CORP18 citations84
US5778441AJul 7, 1998
Method and apparatus for accessing split lock variables in a computer system
INTEL CORP18 citations84
US6114887ASep 5, 2000
Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
INTEL CORP10 citations73
US5901297AMay 4, 1999
Initialization mechanism for symmetric arbitration agents
INTEL CORP9 citations73
US5896513AApr 20, 1999
Computer system providing a universal architecture adaptive to a variety of processor types and bus protocols
INTEL CORP14 citations73