Inventor

LAI KONRAD K

US43 patents

⚠️ This page may combine multiple inventors who share the name “LAI KONRAD K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAI KONRAD K

INTEL CORP

Physical address size selection and page size selection in an address translator

Disabling tag bit recognition and allowing privileged operations to occur in an object-oriented memory protection mechanism

Apparatus and method for caching lock conditions in a multi-processor system

Computer system with distributed bus arbitration scheme for symmetric and priority agents

Exclusive and/or partially inclusive extension cache system and method to minimize swapping therein

Apparatus and method for performing error correction in a multi-processor system

Method and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memory

Object lifetime control in an object-oriented memory protection mechanism

Method and apparatus for performing deferred transactions

Physical address size selection and page size selection in an address translator

Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system

Method and apparatus for performing deferred transactions

Method and apparatus for performing bus transactions in a computer system

Synchronous communication between execution environments in a data processing system employing an object-oriented memory protection mechanism

Apparatus and method for an instruction cache locking scheme

Method and apparatus for performing deferred transactions

Method and apparatus for performing bus transactions in a computer system

Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories

Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories

Memory subsystem wherein a single processor chip controls multiple cache memory chips

Type management and control in an object oriented memory protection mechanism

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

Method and apparatus for retrieving data from a data storage device

Method and apparatus for controlling multiple dice with a single die

Last branch record indicators for transactional memory

Last branch record indicators for transactional memory

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Method and apparatus for retrieving data from a data storage device

Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of target code

Last branch record register for storing taken branch information and transactional memory transaction indicator to be used in transaction execution analysis

Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution

Event counter checkpointing and restoring

RAJWAR RAVI

Processor with last branch record register storing transaction indicator

Transactional memory in out-of-order processors with XABORT having immediate argument

Instruction and logic to test transactional execution status

SRINIVAS SURESH

Method and apparatus to bypass object lock by speculative execution of generated bypass code shell based on bypass failure threshold in managed runtime environment

LACHNER PETER

Debugging parallel software using speculatively executed code sequences in a multiple core environment

KNAUTH LAURA A

Event counter checkpointing and restoring