Inventor

PENG JACK ZEZHONG

US40 patents

⚠️ This page may combine multiple inventors who share the name “PENG JACK ZEZHONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PENG JACK ZEZHONG

KILOPASS TECHNOLOGIES INC

High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline

Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric

High density semiconductor memory cell and memory array using a single transistor having a buried N+ connection

Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric

High density semiconductor memory cell and memory array using a single transistor

Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric

Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric

Field programmable gate array based upon transistor gate oxide breakdown

Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown

Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric

High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown

High density semiconductor memory cell and memory array using a single transistor

Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric

Smart card having memory using a breakdown phenomena in an ultra-thin dielectric

Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage

KILOPASS TECHNOLOGY INC

Memory transistor gate oxide stress release and improved reliability

Electrically programmable fuse bit

Memory transistor gate oxide stress release and improved reliability

Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric

Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric

GATEFIELD CORP

Nonvolatile reprogrammable interconnect cell with FN tunneling in sense

Nonvolatile reprogrammable interconnect cell with programmable buried bitline

Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor

Floating gate FPGA cell with counter-doped select device

CHENGDU PBM TECH LTD

High-density three-dimensional multilayer memory and fabrication method

High-density three-dimensional multilayer memory and fabrication method

Underlying transistor circuit of semiconductor memory and preparation method for the same

Method for manufacturing fully self-aligned high-density 3D multi-layer memory

ADVANCED MICRO DEVICES INC

Method of large angle tilt implant of channel region

Low power CMOS array for a PLD with program and erase using controlled avalanche injection

Memory cell for a programmable logic device (PLD) avoiding pumping programming voltage above an NMOS threshold

KLP INTERNATIONAL LTD

Combination field programmable gate array allowing dynamic reprogrammability

Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit

Programmable logic function generator using non-volatile programmable memory switches

PENG JACK ZEZHONG

Method for fabricating semiconductor memory and the semiconductor memory

Chip packaging fixture using magnetic field for self-alignment

ACTEL CORP

Nonvolatile reprogrammable interconnect cell with FN tunneling device for programming and erase

ZYCAD CORP

Floating gate FGPA cell with separated select device

(unassigned)

Floating gate FPGA cell with select device on drain

CHENGDU KILOWAY ELECTRONICS CO LTD

One time programmable (OTP) memory array and read and write method thereof