Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric

Abstract

A reprogrammable non-volatile memory array and constituent memory cells is disclosed. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes. The memory cells are first programmed by stressing the gate oxide until soft breakdown occurs. The memory cells are then subsequently reprogrammed by increasing the breakdown of the gate oxide.

What is claimed is:  
     
       1. A single polysilicon reprogrammable memory cell useful in a memory array having select and access lines, the memory cell comprising: 
       a MOS field effect transistor having a gate, a gate dielectric underlying the gate, and first and second doped semiconductor regions underlying both the gate dielectric and the gate in a spaced apart relationship to define a channel region there between;  
       a MOS data storage element having a conductive structure, an ultra-thin dielectric underlying the conductive structure, and a first doped semiconductor region underlying both the ultra-thin dielectric and the conductive structure, said ultra-thin dielectric being formed at the same time as said gate dielectric, the first doped semiconductor region of the MOS data storage element being coupled to the first doped semiconductor region of the MOS field effect transistor, said ultra-thin dielectric being capable of being selectively broken down into one of a plurality of breakdown states, wherein each of the MOS data storage elements comprises an inversion-enabled region underlying both the ultra-thin dielectric and the conductive structure and adjacent to the first doped region of the MOS data storage element, further wherein said conductive structure is formed at the same time as said gate;  
       a select line segment coupled to the gate of the MOS field effect transistor;  
       a first access line segment coupled to the second doped semiconductor region of the MOS field effect transistor; and  
       a second access line segment coupled to the conductive structure of the MOS data storage element.  
     
     
       2. A method of operating a single polysilicon reprogrammable memory array comprising a plurality of row lines, a plurality of column lines, at least one source line, and a plurality of memory cells at respective crosspoints of the row lines and column lines, each of the memory cells comprising a MOS field effect transistor coupled in series with a MOS data storage element between one of the column lines and one of the at least one source line, the MOS transistor further having a gate coupled to one of the row lines and the MOS data storage element comprising an ultra-thin dielectric for physical storage of data, said ultra-thin dielectric being capable of being selectively broken down into one of a plurality of breakdown states, further wherein said ultra-thin diectric is formed at the same time as a gate oxide of said MOS field effect transistor the method comprising: 
       applying a first voltage to a selected one of the row lines for turning on each of MOS field effect transistor having the gate thereof coupled to the selected row line;  
       applying a second voltage to a selected one of the column lines; and  
       applying a third voltage to the at least one source line;  
       wherein the second voltage and the third voltage cause a potential difference across the ultra-thin dielectric of the memory cell coupled to the selected row line and the selected column line that is sufficient to break down the ultra-thin dielectric thereof into one of said plurality of breakdown states, further wherein said memory cells are reprogrammed by applying a second potential difference greater than said potential difference across the ultra-thin dielectric to further break down the ultra-thin dielectric into another of said plurality of breakdown states.  
     
     
       3. A method of operating a single polysilicon reprogrammable memory array comprising a plurality of row lines, a plurality of column lines, at least one source line, and a plurality of memory cells at respective crosspoints of the row lines and column lines, each of the memory cells comprising a MOS field effect transistor coupled in series with a MOS data storage element between one of the column lines and one of the at least one source line, the MOS transistor further having a gate coupled to one of the row lines and the MOS data storage element comprising an ultra-thin dielectric for physical storage of data, said ultra-thin dielectric being capable of being selectively broken down into one of a plurality of breakdown states, further wherein said ultra-thin diectric is formed at the same time as a gate oxide of said MOS field effect transistor the method comprising: 
       applying a first voltage to a selected one of the row lines for turning on each of MOS field effect transistor having the gate thereof coupled to the selected row line;  
       applying a second voltage to a selected one of the column lines; and  
       applying a third voltage to the at least one source line;  
       wherein the second voltage and the third voltage cause a potential difference across the ultra-thin dielectric of the memory cell coupled to the selected row line and the selected column line that is sufficient to break down the ultra-thin dielectric thereof into one of said plurality of breakdown states, further wherein said memory cells are reprogrammed by applying said potential difference across the ultra-thin dielectric for a further period of time to further break down the ultra-thin dielectric into another of said plurality of breakdown states.  
     
     
       4. A method of operating a single polysilicon reprogrammable memory array comprising a plurality of row lines, a plurality of column lines, at least one source line, and a plurality of memory cells at respective crosspoints of the row lines and column lines, each of the memory cells comprising a MOS field effect transistor coupled in series with a MOS data storage element between one of the column lines and one of the at least one source line, the MOS transistor further having a gate coupled to one of the row lines and the MOS data storage element comprising an ultra-thin dielectric for physical storage of data, said ultra-thin dielectric being capable of being selectively broken down into one of a plurality of breakdown states, further wherein said ultra-thin diectric is formed at the same time as a gate oxide of said MOS field effect transistor, the method comprising: 
       applying a first voltage to a selected one of the row lines for turning on each of MOS field effect transistor having the gate thereof coupled to the selected row line;  
       applying a second voltage to a selected one of the column lines; and  
       applying a third voltage to the at least one source line;  
       wherein the second voltage and the third voltage cause a potential difference across the ultra-thin dielectric of the memory cell coupled to the selected row line and the selected column line that is sufficient to break down the ultra-thin dielectric thereof into one of said plurality of breakdown states, further wherein said memory cells are reprogrammed by applying a second potential difference across the ultra-thin dielectric for a further period of time to further break down the ultra-thin dielectric into another of said plurality of breakdown states.  
     
     
       5. A method of operating a single polysilicon reprogrammable memory array comprising a plurality of row lines, a plurality of column lines, at least one source line, and a plurality of memory cells at respective crosspoints of the row lines and column lines, each of the memory cells comprising a MOS field effect transistor coupled in series with a MOS data storage element between one of the column lines and one of the at least one source line, the MOS transistor further having a gate coupled to one of the row lines and the MOS data storage element comprising an ultra-thin dielectric for physical storage of data, said ultra-thin dielectric being capable of being selectively broken down into one of a plurality of breakdown states, further wherein said ultra-thin diectric is formed at the same time as a gate oxide of said MOS field effect transistor the method comprising: 
       applying a first voltage to a selected one of the row lines for turning on each of MOS field effect transistor having the gate thereof coupled to the selected row line;  
       applying a second voltage to a selected one of the column lines; and  
       applying a third voltage to the at least one source line;  
       wherein the second voltage and the third voltage cause a potential difference across the ultra-thin dielectric of the memory cell coupled to the selected row line and the selected column line that is sufficient to break down the ultra-thin dielectric thereof into one of said plurality of breakdown states, further wherein said memory cells are reprogrammed by increasing said first voltage to said selected one of the row lines in order to increase the amount of current used to break down the ultra-thin dielectric into another of said plurality of breakdown states.  
     
     
       6. A method of operating a single polysilicon reprogrammable memory array comprising a plurality of row lines, a plurality of column lines, at least one source line, and a plurality of memory cells at respective crosspoints of the row lines and column lines, each of the memory cells comprising a MOS field effect transistor coupled in series with a MOS data storage element between one of the column lines and one of the at least one source line, the MOS transistor further having a gate coupled to one of the row lines and the MOS data storage element comprising an ultra-thin dielectric for physical storage of data, said ultra-thin dielectric being capable of being selectively broken down into one of a plurality of breakdown states, further wherein said ultra-thin diectric is formed at the same time as a gate oxide of said MOS field effect transistor, the method comprising: 
       applying a first voltage to a selected one of the row lines for turning on each of MOS field effect transistor having the gate thereof coupled to the selected row line;  
       applying a second voltage to a selected one of the column lines; and  
       applying a third voltage to the at least one source line;  
       wherein the second voltage and the third voltage cause a potential difference across the ultra-thin dielectric of the memory cell coupled to the selected row line and the selected column line that is sufficient to break down the ultra-thin dielectric thereof into one of said plurality of breakdown states, further wherein said memory cells are read by monitoring an amount of current flowing through said MOS data storage element and determining that a memory cell is programmed if said amount of current is above a predetermined threshold.  
     
     
       7. The method of  claim 6  wherein said memory cells are erased by increasing said predetermined threshold. 
     
     
       8. A single poloysilicon reprogrammable memory array comprising a plurality of row lines, a plurality of column lines, at least one shared line, and a plurality of memory cells at respective crosspoints of the row lines and column lines in the memory, each of the memory cells comprising: 
       a MOS field effect transistor having a gate, a gate dielectric underlying the gate, and first and second doped semiconductor regions underlying both the gate dielectric and the gate in a spaced apart relationship to define a channel region therebetween; and  
       a MOS data storage element having a conductive structure, an ultra-thin dielectric underlying the conductive structure, and a first doped semiconductor region underlying both the ultra-thin dielectric and the conductive structure, wherein said ultra-thin diectric is formed at the same time as said gate dielectric of said MOS field effect transistor, the first doped semiconductor region of the MOS data storage element being coupled to the first doped semiconductor region of the MOS field effect transistor, said ultra-thin dielectric being capable of being selectively broken down into one of a plurality of breakdown states, further wherein each of the MOS data storage elements comprises an inversion-enabled region underling both the ultra-thin dielectric and the conductive structure and adjacent to the first doped region of the MOS data storage element; further wherein said conductive structure is formed at the same time as said gate;  
       wherein one of the column lines is coupled to the second doped semiconductor region of the MOS field effect transistor or to the conductive structure of the MOS data storage element, and one of the at least one shared lines is coupled to the conductive structure of the MOS data storage element or to the second doped semiconductor region of the MOS field effect transistor.  
     
     
       9. The memory array of  claim 8  wherein each of the MOS data storage elements comprises a second doped region underling both the ultra-thin dielectric and the conductive structure and integrated with the first doped region of the MOS data storage element. 
     
     
       10. The memory array of  claim 8 , wherein the gate dielectric of the MOS field effect transistors and the ultra-thin dielectric of the MOS data storage elements are formed from a common layer of ultra-thin gate oxide. 
     
     
       11. A single polysilicon reprogrammable memory array comprising a plurality of row lines, a plurality of column lines, at least one shared line, and a plurality of memory cells at respective crosspoints of the row lines and column lines in the memory, each of the memory cells comprising a select transistor coupled in series with a data storage element between one of the column lines and one of the at least one shared line, the select transistor further having a gate coupled to one of the row lines and the data storage element comprising an ultra-thin dielectric for physical storage of data, said ultra-thin dielectric being capable of being selectively broken down into one of a plurality of breakdown states, further wherein said ultra-thin diectric is formed at the same time as a gate oxide of said MOS field effect transistor, wherein the data storage element is a MOS half-transistor. 
     
     
       12. A single polysilicon reprogrammable non-volatile memory cell comprising a select transistor coupled in series with a data storage element, the data storage element comprising a conductive structure, an ultra-thin dielectric underlying said conductive for physical storage of data, and a first doped semiconductor region underlying both the ultra-thin dielectric and the conductive structure, said select transistor having a gate that is controllable to address said memory cell, said ultra-thin dielectric being capable of being selectively broken down into one of a plurality of breakdown states, further wherein said conductive structure is formed at the same time as said gate, wherein the data storage element is a MOS half-transistor. 
     
     
       13. The memory cell of  claim 12  wherein said memory cell is programmed by breaking down said ultra-thin dielectric into one of said plurality of breakdown states by applying a voltage between said conductive structure and said first doped semiconductor region. 
     
     
       14. The memory cell of  claim 13  wherein said memory cell is read by sensing a current through said data storage element during application of a voltage between said conductive structure and said first doped semiconductor region. 
     
     
       15. The memory cell of  claim 12  further including means for applying a variable voltage to the gate of said select transistor to selectively break down said ultra-thin dielectric into one of a plurality of breakdown states. 
     
     
       16. The memory cell of  claim 12  further including current sensing means for determining the amount of current flowing through said data storage element, said current sensing means indicating that the memory cell is programmed if the amount of current is above a predetermined threshold, said memory cell being logically erasing by changing said predetermined threshold.