Inventor

LASKY JEROME B

44 patents

⚠️ This page may combine multiple inventors who share the name “LASKY JEROME B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LASKY JEROME B

IBM

Fin field effect transistor with self-aligned gate

Double planar gated SOI MOSFET structure

Semiconductor memory cell and memory array with inversion layer

Double planar gated SOI MOSFET structure

Power distribution design method for stacked flip-chip packages

Plug strap process utilizing selective nitride and oxide etches

Method of forming metal-strapped polysilicon gate electrode for FET device

Method of improving silicon-on-insulator uniformity

Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor

Oxidation of silicon nitride in semiconductor devices

Method of producing a thin silicon-on-insulator layer

Emissivity independent temperature measurement systems

Deep trench contact and isolation of buried photodetectors

Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet

Power distribution design method for stacked flip-chip packages

Method and structure for creating high density buried contact for use with SOI processes for high performance logic

Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET

Recessed gate for an image sensor

Method for limiting divot formation in post shallow trench isolation processes

Boron out-diffused surface strap process

Method of self-aligning a trench isolation structure to an implanted well region

Method of fabricating silicon-on-insulator transistors with a shared element

Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step

Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer

Semiconductor temperature monitor

Plasma etch pre-silicide clean

Integrated cobalt silicide process for semiconductor devices

Method of laser annealing of subsurface ion implanted regions

Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch

Method of forming planar isolation and substrate contacts in SIMOX-SOI.

Pixel sensor cell having reduced pinning layer barrier potential and method thereof

Process for making low-leakage contacts

Recessed gate for a CMOS image sensor

Semiconductor temperature monitor

STI fill for SOI which makes SOI inspectable

Method of forming pixel sensor cell having reduced pinning layer barrier potential

FIN field effect transistor with self-aligned gate

Method for semiconductor fabrication

Test structure and method for detecting and studying crystal lattice dislocation defects in integrated circuit devices

Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch

Integrated cobalt silicide process for semiconductor devices

Buried butted contact and method for fabricating

Buried butted contact and method for fabricating

US ENERGY

Method of preparing a thermoluminescent phosphor