FIN field effect transistor with self-aligned gate

Abstract

The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

1. A double-gated/double-channel FIN metal oxide semiconductor field effect transistor (MOSFET) comprising:
 a bottom Si-containing layer; 
 an insulating region present atop said bottom Si-containing layer, said insulating region having at least one partial opening therein; 
 a gate region formed in said partial opening, said gate region comprising two regions of gate conductor that are separated from vertical fin-shaped silicon-containing channel regions by an insulating film, said insulating film comprising a gate dielectric and having opposite vertical surfaces adjacent to the vertical fin-shaped silicon-containing channel regions; 
 source/drain diffusion regions abutting said gate region, said source/drain diffusion regions having junctions that are self-aligned to the vertical fin-shaped silicon-containing channels regions and the gate region; and 
 insulating spacers in said partial opening that separate the gate region and the source/drain diffusion regions formed orthogonal to said insulating film; 
 wherein said gate region is between said insulating spacers; and 
 wherein the gate region is self-aligned to the source/drain diffusion regions and the vertical fin-shaped silicon-containing channel regions. 
 
     
     
       2. The FIN MOSFET of  claim 1  wherein said insulating region includes an insulating layer of an SOI material. 
     
     
       3. The FIN MOSFET of  claim 2  wherein said partial opening exposes a portion of said insulating layer of said SOI material. 
     
     
       4. The FIN MOSFET of  claim 1  wherein said insulating film is formed surrounding a portion of a Si-containing layer. 
     
     
       5. The FIN MOSFET of  claim 4  wherein the gate dielectric of said insulating film is comprised of an oxide, a nitride, an oxynitride or any combination or multilayer thereof. 
     
     
       6. The FIN MOSFET of  claim 1  wherein said regions of gate conductor are each comprised of polysilicon, amorphous Si, a conductive elemental metal, an alloy of a conductive elemental metal, a nitride or silicide of a conductive elemental metal or multilayers thereof. 
     
     
       7. The FIN MOSFET of  claim 1  further comprising salicide regions formed atop said source/drain diffusion regions. 
     
     
       8. The FIN MOSFET of  claim 1  wherein said source/drain diffusion regions are formed in a portion of a patterned Si-containing layer.