Inventor

TAKASE SATORU

JP46 patents

⚠️ This page may combine multiple inventors who share the name “TAKASE SATORU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAKASE SATORU

TOSHIBA KK

Systems and methods for data transfers between memory cells

Semiconductor device with flexible redundancy system

Semiconductor storage device

Semiconductor memory integrated circuit employing a redundant circuit system for compensating for defectiveness

Semiconductor memory

Dynamic random access memory with complementary bit lines and capacitor common line

Resistance change memory device

Semiconductor device with flexible redundancy system

Dynamic random access memory device and semiconductor integrated circuit device

Semiconductor device with flexible redundancy system

Dynamic type memory

Dynamic type memory

Semiconductor memory device

Semiconductor memory having memory cell units each including cascade-connected MOS transistors

Semiconductor storage device

Semiconductor memory device and semiconductor memory system

Resistance change memory device

Nonvolatile semiconductor memory device and method of driving the same

System and method for lock detection of a phase-locked loop circuit

Semiconductor integrated circuit having a built-in data storage circuit for nonvolatile storage of control data

Semiconductor device with flexible redundancy system

Semiconductor device with flexible redundancy system

Dynamic random access memory device and semiconductor integrated circuit device

Semiconductor memory for logic-hybrid memory

Semiconductor memory device and method of controlling the same

Dynamic memory

Multilayer wiring structure for memory circuit

Systems and methods for increasing yield of devices having cache memories by inhibiting use of defective cache entries

Systems and methods for improving memory reliability by selectively enabling word line signals

Systems and methods for data transfers between memory cells

System and method for PLL control

System and method for phase-locked loop leak compensation

Semiconductor device with flexible redundancy system

Semiconductor memory for logic-hybrid memory

Dynamic type memory

System and method for configuring conductors within an integrated circuit to reduce impedance variation caused by connection bumps

Semiconductor device with flexible redundancy system

Semiconductor memory for logic-hybrid memory

Semiconductor memory for logic-hybrid memory

Systems and methods for improving memory reliability

Semiconductor memory device and driving method thereof

TAKASE SATORU

Resistance change memory device

Semiconductor memory device

Resistance change memory device

OKUKAWA YUKI

Semiconductor memory device

HOSONO KOJI

Semiconductor memory device